Module Definition
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Module : adc_ctrl_fsm_sva
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva 100.00 100.00



Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.75 100.00 100.00 100.00 98.73 100.00 u_adc_ctrl_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : adc_ctrl_fsm_sva
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 11 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 11 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FsmDebugOut_A 32254137 32171668 0 0
FsmStateHwReset_A 1200 1200 0 0
FsmStateSwReset_A 32254137 6568 0 0
LpSampleCntHwReset_A 1200 1200 0 0
LpSampleCntSwReset_A 32254137 6568 0 0
NpSampleCntHwReset_A 1200 1200 0 0
NpSampleCntSwReset_A 32254137 6568 0 0
PwrupTimerCntHwReset_A 1200 1200 0 0
PwrupTimerCntSwReset_A 32254137 6568 0 0
WakeupTimerCntHwReset_A 1200 1200 0 0
WakeupTimerCntSwReset_A 32254137 6568 0 0


FsmDebugOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 32254137 32171668 0 0
T1 96857 96762 0 0
T2 97445 97375 0 0
T3 97861 97800 0 0
T4 8926 8868 0 0
T5 37602 37504 0 0
T6 51 1 0 0
T7 6245 6173 0 0
T8 33602 33506 0 0
T9 67464 67390 0 0
T10 65795 65727 0 0

FsmStateHwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1200 1200 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

FsmStateSwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 32254137 6568 0 0
T1 96857 23 0 0
T2 97445 24 0 0
T3 97861 26 0 0
T4 8926 0 0 0
T5 37602 6 0 0
T6 51 0 0 0
T7 6245 0 0 0
T8 33602 7 0 0
T9 67464 15 0 0
T10 65795 17 0 0
T22 0 4 0 0
T23 0 23 0 0
T25 0 14 0 0

LpSampleCntHwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1200 1200 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

LpSampleCntSwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 32254137 6568 0 0
T1 96857 23 0 0
T2 97445 24 0 0
T3 97861 26 0 0
T4 8926 0 0 0
T5 37602 6 0 0
T6 51 0 0 0
T7 6245 0 0 0
T8 33602 7 0 0
T9 67464 15 0 0
T10 65795 17 0 0
T22 0 4 0 0
T23 0 23 0 0
T25 0 14 0 0

NpSampleCntHwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1200 1200 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

NpSampleCntSwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 32254137 6568 0 0
T1 96857 23 0 0
T2 97445 24 0 0
T3 97861 26 0 0
T4 8926 0 0 0
T5 37602 6 0 0
T6 51 0 0 0
T7 6245 0 0 0
T8 33602 7 0 0
T9 67464 15 0 0
T10 65795 17 0 0
T22 0 4 0 0
T23 0 23 0 0
T25 0 14 0 0

PwrupTimerCntHwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1200 1200 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

PwrupTimerCntSwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 32254137 6568 0 0
T1 96857 23 0 0
T2 97445 24 0 0
T3 97861 26 0 0
T4 8926 0 0 0
T5 37602 6 0 0
T6 51 0 0 0
T7 6245 0 0 0
T8 33602 7 0 0
T9 67464 15 0 0
T10 65795 17 0 0
T22 0 4 0 0
T23 0 23 0 0
T25 0 14 0 0

WakeupTimerCntHwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1200 1200 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

WakeupTimerCntSwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 32254137 6568 0 0
T1 96857 23 0 0
T2 97445 24 0 0
T3 97861 26 0 0
T4 8926 0 0 0
T5 37602 6 0 0
T6 51 0 0 0
T7 6245 0 0 0
T8 33602 7 0 0
T9 67464 15 0 0
T10 65795 17 0 0
T22 0 4 0 0
T23 0 23 0 0
T25 0 14 0 0

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