Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1281	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1298	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1418	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1438	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1334	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1395	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1296	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1474	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1436	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1290	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1418	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1250	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1396	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1429	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1380	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1311	0	0
adc_en_ctl_rd_A	2147483647	969	0	0
adc_fsm_rst_rd_A	2147483647	872	0	0
adc_intr_ctl_rd_A	2147483647	1249	0	0
adc_lp_sample_ctl_rd_A	2147483647	918	0	0
adc_pd_ctl_rd_A	2147483647	1256	0	0
adc_sample_ctl_rd_A	2147483647	852	0	0
adc_wakeup_ctl_rd_A	2147483647	1009	0	0
intr_enable_rd_A	2147483647	1331	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1281	0	0
T11	153703	16	0	0
T12	818394	12	0	0
T13	0	12	0	0
T14	0	24	0	0
T15	0	11	0	0
T16	0	9	0	0
T17	0	33	0	0
T18	0	21	0	0
T19	0	19	0	0
T20	0	41	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1298	0	0
T11	153703	4	0	0
T12	818394	15	0	0
T13	0	20	0	0
T14	0	21	0	0
T15	0	25	0	0
T16	0	17	0	0
T17	0	36	0	0
T18	0	37	0	0
T19	0	12	0	0
T20	0	20	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1418	0	0
T11	153703	13	0	0
T12	818394	13	0	0
T13	0	19	0	0
T14	0	31	0	0
T15	0	25	0	0
T16	0	21	0	0
T17	0	45	0	0
T18	0	26	0	0
T19	0	22	0	0
T20	0	24	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1438	0	0
T11	153703	12	0	0
T12	818394	23	0	0
T13	0	7	0	0
T14	0	26	0	0
T15	0	17	0	0
T16	0	18	0	0
T17	0	37	0	0
T18	0	27	0	0
T19	0	21	0	0
T20	0	29	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1334	0	0
T11	153703	12	0	0
T12	818394	13	0	0
T13	0	20	0	0
T14	0	15	0	0
T15	0	12	0	0
T16	0	10	0	0
T17	0	40	0	0
T18	0	35	0	0
T19	0	22	0	0
T20	0	28	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1395	0	0
T11	153703	9	0	0
T12	818394	16	0	0
T13	0	16	0	0
T14	0	34	0	0
T15	0	23	0	0
T16	0	30	0	0
T17	0	25	0	0
T18	0	39	0	0
T19	0	11	0	0
T20	0	41	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1296	0	0
T11	153703	14	0	0
T12	818394	12	0	0
T13	0	11	0	0
T14	0	42	0	0
T15	0	16	0	0
T16	0	30	0	0
T17	0	37	0	0
T18	0	10	0	0
T19	0	24	0	0
T20	0	42	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1474	0	0
T11	153703	15	0	0
T12	818394	21	0	0
T13	0	20	0	0
T14	0	17	0	0
T15	0	29	0	0
T16	0	27	0	0
T17	0	39	0	0
T18	0	55	0	0
T19	0	18	0	0
T20	0	46	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1436	0	0
T11	153703	11	0	0
T12	818394	25	0	0
T13	0	23	0	0
T14	0	23	0	0
T15	0	22	0	0
T16	0	21	0	0
T17	0	25	0	0
T18	0	26	0	0
T19	0	13	0	0
T20	0	60	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1290	0	0
T11	153703	11	0	0
T12	818394	21	0	0
T13	0	14	0	0
T14	0	29	0	0
T15	0	15	0	0
T16	0	28	0	0
T17	0	36	0	0
T18	0	27	0	0
T19	0	31	0	0
T20	0	47	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1418	0	0
T11	153703	22	0	0
T12	818394	20	0	0
T13	0	21	0	0
T14	0	37	0	0
T15	0	35	0	0
T16	0	14	0	0
T17	0	23	0	0
T18	0	34	0	0
T19	0	15	0	0
T20	0	25	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1250	0	0
T11	153703	13	0	0
T12	818394	8	0	0
T13	0	10	0	0
T14	0	31	0	0
T15	0	17	0	0
T16	0	18	0	0
T17	0	34	0	0
T18	0	29	0	0
T19	0	21	0	0
T20	0	29	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1396	0	0
T11	153703	16	0	0
T12	818394	8	0	0
T13	0	19	0	0
T14	0	18	0	0
T15	0	25	0	0
T16	0	24	0	0
T17	0	40	0	0
T18	0	29	0	0
T19	0	24	0	0
T20	0	42	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1429	0	0
T11	153703	8	0	0
T12	818394	12	0	0
T13	0	26	0	0
T14	0	38	0	0
T15	0	24	0	0
T16	0	12	0	0
T17	0	40	0	0
T18	0	28	0	0
T19	0	16	0	0
T20	0	42	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1380	0	0
T11	153703	16	0	0
T12	818394	3	0	0
T13	0	23	0	0
T14	0	18	0	0
T15	0	22	0	0
T16	0	35	0	0
T17	0	31	0	0
T18	0	32	0	0
T19	0	33	0	0
T20	0	42	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1311	0	0
T11	153703	14	0	0
T12	818394	10	0	0
T13	0	22	0	0
T14	0	40	0	0
T15	0	16	0	0
T16	0	16	0	0
T17	0	31	0	0
T18	0	24	0	0
T19	0	20	0	0
T20	0	31	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	969	0	0
T11	153703	7	0	0
T12	818394	19	0	0
T13	0	36	0	0
T14	0	36	0	0
T15	0	27	0	0
T16	0	10	0	0
T17	0	29	0	0
T18	0	13	0	0
T19	0	22	0	0
T20	0	42	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	872	0	0
T11	153703	16	0	0
T12	818394	16	0	0
T13	0	24	0	0
T14	0	36	0	0
T15	0	19	0	0
T16	0	7	0	0
T17	0	27	0	0
T18	0	28	0	0
T19	0	28	0	0
T20	0	53	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1249	0	0
T11	153703	15	0	0
T12	818394	19	0	0
T13	0	17	0	0
T14	0	33	0	0
T15	0	12	0	0
T16	0	5	0	0
T17	0	32	0	0
T18	0	41	0	0
T19	0	17	0	0
T20	0	26	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	918	0	0
T11	153703	12	0	0
T12	818394	16	0	0
T13	0	20	0	0
T14	0	36	0	0
T15	0	26	0	0
T16	0	15	0	0
T17	0	37	0	0
T18	0	32	0	0
T19	0	18	0	0
T20	0	55	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1256	0	0
T11	153703	15	0	0
T12	818394	11	0	0
T13	0	11	0	0
T14	0	22	0	0
T15	0	15	0	0
T16	0	15	0	0
T17	0	30	0	0
T18	0	39	0	0
T19	0	22	0	0
T20	0	42	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	852	0	0
T11	153703	24	0	0
T12	818394	12	0	0
T13	0	23	0	0
T14	0	22	0	0
T15	0	26	0	0
T16	0	18	0	0
T17	0	43	0	0
T18	0	35	0	0
T19	0	19	0	0
T20	0	42	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1009	0	0
T11	153703	5	0	0
T12	818394	23	0	0
T13	0	14	0	0
T14	0	23	0	0
T15	0	24	0	0
T16	0	32	0	0
T17	0	27	0	0
T18	0	26	0	0
T19	0	22	0	0
T20	0	41	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1331	0	0
T11	153703	22	0	0
T12	818394	16	0	0
T13	0	30	0	0
T14	0	57	0	0
T15	0	28	0	0
T16	0	17	0	0
T21	378260	0	0	0
T22	430696	0	0	0
T23	155744	0	0	0
T24	267959	0	0	0
T25	773054	0	0	0
T26	144418	0	0	0
T27	271803	0	0	0
T28	162803	0	0	0
T29	0	1	0	0
T30	0	22	0	0
T31	0	10	0	0
T32	0	39	0	0