Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1230758	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1203242

1

T1

6301

T2

6315

T3

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2133632	1			T1	12100		T2	12035		T6	850
values[0x0]	149647	1			T1	384		T2	409		T3	23
values[0x1]	150721	1			T1	399		T2	416		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	985791	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1448209

1

T1

7608

T2

7621

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8621	1			T1	9		T2	40		T9	16
valid_sources[0x01]	7786	1			T1	17		T2	46		T9	17
valid_sources[0x02]	8069	1			T1	10		T2	48		T4	1
valid_sources[0x03]	12524	1			T2	60		T9	14		T11	6
valid_sources[0x04]	12024	1			T1	13		T2	66		T9	5
valid_sources[0x05]	8006	1			T1	20		T2	56		T9	14
valid_sources[0x06]	7358	1			T1	35		T2	45		T9	7
valid_sources[0x07]	8025	1			T1	26		T2	38		T9	9
valid_sources[0x08]	7317	1			T1	11		T2	36		T9	5
valid_sources[0x09]	7789	1			T1	16		T2	53		T9	21
valid_sources[0x0a]	11521	1			T1	25		T2	58		T9	9
valid_sources[0x0b]	11872	1			T1	4275		T2	38		T9	12
valid_sources[0x0c]	11906	1			T1	41		T2	42		T9	9
valid_sources[0x0d]	6869	1			T1	12		T2	42		T9	13
valid_sources[0x0e]	7339	1			T1	5		T2	70		T9	9
valid_sources[0x0f]	7543	1			T1	11		T2	49		T9	10
valid_sources[0x10]	7395	1			T1	4		T2	55		T9	15
valid_sources[0x11]	8445	1			T1	20		T2	53		T15	1
valid_sources[0x12]	11550	1			T1	12		T2	40		T9	9
valid_sources[0x13]	8660	1			T1	47		T2	53		T15	1
valid_sources[0x14]	7127	1			T1	11		T2	43		T9	12
valid_sources[0x15]	7323	1			T1	16		T2	57		T9	15
valid_sources[0x16]	8698	1			T1	8		T2	66		T9	10
valid_sources[0x17]	7432	1			T1	31		T2	48		T9	9
valid_sources[0x18]	8648	1			T1	10		T2	45		T9	9
valid_sources[0x19]	11079	1			T1	3		T2	55		T3	37
valid_sources[0x1a]	10135	1			T1	10		T2	61		T9	10
valid_sources[0x1b]	7258	1			T1	12		T2	55		T4	1
valid_sources[0x1c]	7560	1			T1	13		T2	56		T9	9
valid_sources[0x1d]	14302	1			T1	9		T2	56		T9	11
valid_sources[0x1e]	11213	1			T1	37		T2	58		T4	2
valid_sources[0x1f]	10443	1			T1	17		T2	42		T9	9
valid_sources[0x20]	7522	1			T1	2		T2	67		T9	11
valid_sources[0x21]	8048	1			T1	3		T2	74		T9	11
valid_sources[0x22]	11576	1			T1	12		T2	58		T9	10
valid_sources[0x23]	20256	1			T1	10		T2	42		T9	10
valid_sources[0x24]	17346	1			T1	4		T2	57		T9	21
valid_sources[0x25]	8351	1			T1	8		T2	57		T9	15
valid_sources[0x26]	11602	1			T1	6		T2	56		T9	12
valid_sources[0x27]	11347	1			T1	22		T2	51		T9	16
valid_sources[0x28]	7542	1			T1	51		T2	35		T9	16
valid_sources[0x29]	8743	1			T1	10		T2	59		T9	9
valid_sources[0x2a]	10317	1			T1	22		T2	48		T9	8
valid_sources[0x2b]	7194	1			T1	5		T2	30		T9	19
valid_sources[0x2c]	7505	1			T1	41		T2	59		T9	19
valid_sources[0x2d]	7132	1			T1	10		T2	55		T4	1
valid_sources[0x2e]	7370	1			T1	18		T2	44		T9	14
valid_sources[0x2f]	9537	1			T1	29		T2	62		T9	5
valid_sources[0x30]	12584	1			T1	13		T2	57		T4	2
valid_sources[0x31]	10059	1			T1	14		T2	68		T9	11
valid_sources[0x32]	7689	1			T1	14		T2	50		T9	12
valid_sources[0x33]	8952	1			T1	25		T2	49		T9	12
valid_sources[0x34]	8296	1			T1	56		T2	33		T9	8
valid_sources[0x35]	12265	1			T1	14		T2	82		T9	8
valid_sources[0x36]	8243	1			T1	16		T2	45		T4	1
valid_sources[0x37]	7533	1			T1	7		T2	43		T9	14
valid_sources[0x38]	8634	1			T1	20		T2	57		T9	14
valid_sources[0x39]	7708	1			T2	70		T9	7		T11	3
valid_sources[0x3a]	7634	1			T1	10		T2	58		T9	12
valid_sources[0x3b]	12838	1			T1	4		T2	52		T9	10
valid_sources[0x3c]	7283	1			T1	8		T2	52		T9	14
valid_sources[0x3d]	8361	1			T1	16		T2	65		T9	6
valid_sources[0x3e]	11087	1			T1	36		T2	39		T9	11
valid_sources[0x3f]	15034	1			T1	26		T2	45		T4	2
valid_sources[0x40]	8552	1			T1	1		T2	38		T9	12
valid_sources[0x41]	8109	1			T1	20		T2	57		T4	1
valid_sources[0x42]	9752	1			T1	45		T2	42		T9	10
valid_sources[0x43]	7566	1			T1	28		T2	56		T9	11
valid_sources[0x44]	8110	1			T1	12		T2	40		T9	12
valid_sources[0x45]	7742	1			T1	10		T2	43		T9	11
valid_sources[0x46]	7649	1			T1	7		T2	57		T9	12
valid_sources[0x47]	20724	1			T1	3		T2	61		T9	12
valid_sources[0x48]	12647	1			T1	9		T2	44		T9	7
valid_sources[0x49]	8214	1			T1	2		T2	70		T9	14
valid_sources[0x4a]	8667	1			T1	24		T2	40		T9	13
valid_sources[0x4b]	13696	1			T1	29		T2	65		T9	11
valid_sources[0x4c]	11838	1			T1	17		T2	46		T9	4
valid_sources[0x4d]	7500	1			T1	10		T2	46		T4	2
valid_sources[0x4e]	7945	1			T1	35		T2	44		T9	12
valid_sources[0x4f]	12242	1			T1	19		T2	42		T9	8
valid_sources[0x50]	7193	1			T1	12		T2	49		T9	10
valid_sources[0x51]	8458	1			T1	13		T2	49		T9	6
valid_sources[0x52]	7494	1			T1	15		T2	47		T9	9
valid_sources[0x53]	7533	1			T1	5		T2	55		T9	13
valid_sources[0x54]	8170	1			T1	21		T2	53		T9	15
valid_sources[0x55]	10768	1			T1	7		T2	43		T9	12
valid_sources[0x56]	10211	1			T1	15		T2	60		T9	14
valid_sources[0x57]	11581	1			T1	6		T2	39		T9	12
valid_sources[0x58]	16098	1			T1	10		T2	45		T9	18
valid_sources[0x59]	7051	1			T1	6		T2	43		T9	13
valid_sources[0x5a]	7336	1			T1	48		T2	36		T4	1
valid_sources[0x5b]	12108	1			T1	6		T2	65		T9	5
valid_sources[0x5c]	11541	1			T1	13		T2	48		T9	13
valid_sources[0x5d]	8805	1			T1	28		T2	69		T9	12
valid_sources[0x5e]	7591	1			T1	8		T2	57		T9	11
valid_sources[0x5f]	7378	1			T1	53		T2	61		T15	1
valid_sources[0x60]	7334	1			T1	17		T2	53		T9	12
valid_sources[0x61]	7368	1			T1	10		T2	73		T9	10
valid_sources[0x62]	8591	1			T1	30		T2	64		T9	19
valid_sources[0x63]	10793	1			T1	11		T2	41		T9	9
valid_sources[0x64]	7125	1			T1	23		T2	60		T9	8
valid_sources[0x65]	10689	1			T1	16		T2	42		T9	10
valid_sources[0x66]	7903	1			T2	40		T9	12		T10	66
valid_sources[0x67]	10000	1			T1	39		T2	63		T9	10
valid_sources[0x68]	12004	1			T1	4358		T2	61		T9	9
valid_sources[0x69]	8585	1			T1	20		T2	45		T9	11
valid_sources[0x6a]	8469	1			T1	31		T2	54		T4	1
valid_sources[0x6b]	13525	1			T1	14		T2	49		T9	13
valid_sources[0x6c]	8557	1			T1	18		T2	48		T9	13
valid_sources[0x6d]	8367	1			T1	8		T2	33		T4	1
valid_sources[0x6e]	7815	1			T1	4		T2	30		T8	138
valid_sources[0x6f]	10191	1			T1	23		T2	47		T9	9
valid_sources[0x70]	8303	1			T1	3		T2	41		T9	13
valid_sources[0x71]	11303	1			T1	6		T2	41		T9	5
valid_sources[0x72]	7505	1			T1	31		T2	35		T9	16
valid_sources[0x73]	12494	1			T1	34		T2	38		T9	11
valid_sources[0x74]	7091	1			T1	3		T2	49		T4	2
valid_sources[0x75]	7050	1			T1	30		T2	54		T9	8
valid_sources[0x76]	9377	1			T1	5		T2	39		T9	15
valid_sources[0x77]	7864	1			T1	22		T2	51		T9	11
valid_sources[0x78]	7362	1			T1	24		T2	60		T9	7
valid_sources[0x79]	15840	1			T1	35		T2	42		T7	7
valid_sources[0x7a]	7216	1			T1	19		T2	49		T9	9
valid_sources[0x7b]	8274	1			T1	58		T2	60		T9	8
valid_sources[0x7c]	8611	1			T1	13		T2	34		T9	10
valid_sources[0x7d]	7237	1			T1	33		T2	48		T9	11
valid_sources[0x7e]	7929	1			T1	5		T2	56		T9	9
valid_sources[0x7f]	10630	1			T2	62		T9	11		T11	978
valid_sources[0x80]	7309	1			T2	55		T9	11		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1063291

1

T1

6012

T2

5990

T6

412

values[0x0]

all_enables

biggest_size

81302

1

T1

181

T2

212

T3

12

values[0x1]

all_enables

biggest_size

58649

1

T1

108

T2

113

T3

7