Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29667	1			T1	14		T2	26		T5	236
auto[PWRUP]	108	1			T5	2		T59	2		T41	1
auto[ONEST_0]	58	1			T5	1		T38	1		T59	1
auto[ONEST_021]	15	1			T42	1		T200	1		T201	1
auto[ONEST_1]	86	1			T38	1		T58	3		T57	2
auto[ONEST_DONE]	7	1			T41	1		T202	1		T203	1
auto[LP_0]	127	1			T5	3		T38	1		T39	1
auto[LP_021]	32	1			T56	1		T57	2		T60	1
auto[LP_1]	141	1			T5	1		T38	2		T39	1
auto[LP_EVAL]	74	1			T5	1		T39	1		T59	1
auto[LP_SLP]	532	1			T5	9		T38	10		T39	2
auto[LP_PWRUP]	21	1			T41	1		T58	1		T44	1
auto[NP_0]	183	1			T5	1		T38	1		T39	2
auto[NP_021]	38	1			T56	1		T42	3		T58	2
auto[NP_1]	159	1			T5	2		T59	2		T41	2
auto[NP_EVAL]	35	1			T59	1		T56	2		T42	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T204

1

T205

1

T206

1

min

29107

1

T1

14

T2

26

T5

230

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29111	1			T1	14		T2	26		T5	230
pow[0x1]	7	1			T207	1		T208	1		T209	1
pow[0x2]	19	1			T5	1		T58	1		T210	1
pow[0x3]	40	1			T59	1		T41	1		T34	1
pow[0x4]	64	1			T5	2		T38	2		T59	2
pow[0x5]	162	1			T5	3		T39	1		T59	3
pow[0x6]	284	1			T5	4		T38	7		T59	3
pow[0x7]	542	1			T5	7		T39	6		T59	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

229

1

T5

2

T38

6

T59

2

min

28616

1

T1

14

T2

26

T5

221

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28616	1			T1	14		T2	26		T5	221
pow[0x1]	1	1			T211	1		-	-		-	-
pow[0x6]	1	1			T212	1		-	-		-	-
pow[0x7]	1	1			T213	1		-	-		-	-
pow[0x8]	8	1			T5	1		T60	1		T214	1
pow[0x9]	9	1			T5	1		T215	1		T216	1
pow[0xa]	14	1			T202	1		T201	1		T212	1
pow[0xb]	41	1			T56	1		T42	2		T64	1
pow[0xc]	81	1			T41	3		T56	1		T58	4
pow[0xd]	140	1			T5	2		T39	2		T59	2
pow[0xe]	281	1			T5	1		T38	4		T39	2
pow[0xf]	597	1			T5	10		T38	10		T39	2