Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2332	1			T5	10		T38	29		T39	15
auto[PWRUP]	137	1			T5	1		T38	1		T59	2
auto[ONEST_0]	83	1			T5	1		T38	2		T39	1
auto[ONEST_021]	19	1			T41	1		T64	1		T232	1
auto[ONEST_1]	92	1			T38	2		T39	1		T41	1
auto[ONEST_DONE]	4	1			T216	1		T35	1		T345	2
auto[LP_0]	156	1			T5	2		T38	3		T39	1
auto[LP_021]	20	1			T42	1		T221	1		T201	1
auto[LP_1]	153	1			T5	2		T38	1		T59	3
auto[LP_EVAL]	55	1			T5	1		T39	1		T58	1
auto[LP_SLP]	542	1			T5	4		T38	5		T39	2
auto[LP_PWRUP]	37	1			T42	1		T57	1		T44	2
auto[NP_0]	240	1			T5	2		T38	6		T39	2
auto[NP_021]	56	1			T39	1		T59	1		T40	1
auto[NP_1]	245	1			T38	3		T39	4		T59	2
auto[NP_EVAL]	31	1			T59	1		T41	1		T58	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T210

1

T64

1

T207

1

min

1958

1

T5

5

T38

21

T39

17

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1973	1			T5	5		T38	21		T39	17
pow[0x1]	9	1			T39	1		T64	1		T191	1
pow[0x2]	24	1			T42	1		T58	2		T210	2
pow[0x3]	45	1			T42	1		T58	1		T43	1
pow[0x4]	80	1			T38	2		T56	1		T58	2
pow[0x5]	141	1			T5	1		T38	3		T39	2
pow[0x6]	273	1			T5	2		T38	4		T39	2
pow[0x7]	537	1			T5	4		T38	6		T39	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

189

1

T38

4

T39

1

T59

3

min

1361

1

T38

16

T39

13

T59

4

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1364	1			T38	16		T39	13		T59	4
pow[0x1]	17	1			T39	1		T73	1		T232	1
pow[0x2]	35	1			T38	1		T41	1		T27	1
pow[0x3]	42	1			T39	2		T40	1		T43	3
pow[0x4]	55	1			T38	2		T40	2		T43	2
pow[0x6]	1	1			T346	1		-	-		-	-
pow[0x7]	2	1			T215	1		T203	1		-	-
pow[0x8]	6	1			T207	1		T347	2		T348	1
pow[0x9]	6	1			T56	1		T207	1		T349	1
pow[0xa]	17	1			T38	1		T210	1		T60	1
pow[0xb]	41	1			T59	1		T56	1		T42	1
pow[0xc]	80	1			T38	1		T59	1		T41	2
pow[0xd]	164	1			T5	1		T38	1		T39	1
pow[0xe]	309	1			T5	2		T38	5		T39	2
pow[0xf]	608	1			T5	4		T38	8		T39	3