Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1914	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1683	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1751	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1978	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1883	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1985	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1663	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1903	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1881	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1707	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1677	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1936	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1724	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1984	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1993	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1770	0	0
adc_en_ctl_rd_A	2147483647	1531	0	0
adc_fsm_rst_rd_A	2147483647	1323	0	0
adc_intr_ctl_rd_A	2147483647	1746	0	0
adc_lp_sample_ctl_rd_A	2147483647	1430	0	0
adc_pd_ctl_rd_A	2147483647	1458	0	0
adc_sample_ctl_rd_A	2147483647	1348	0	0
adc_wakeup_ctl_rd_A	2147483647	1529	0	0
intr_enable_rd_A	2147483647	1866	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1914	0	0
T17	351374	11	0	0
T18	177890	14	0	0
T19	0	41	0	0
T20	0	47	0	0
T21	0	26	0	0
T22	0	41	0	0
T23	0	11	0	0
T24	0	29	0	0
T25	0	24	0	0
T26	0	35	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1683	0	0
T17	351374	17	0	0
T18	177890	11	0	0
T19	0	33	0	0
T20	0	34	0	0
T21	0	25	0	0
T22	0	43	0	0
T23	0	9	0	0
T24	0	34	0	0
T25	0	44	0	0
T26	0	44	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1751	0	0
T17	351374	18	0	0
T18	177890	0	0	0
T19	0	31	0	0
T20	0	36	0	0
T21	0	18	0	0
T22	0	38	0	0
T23	0	18	0	0
T24	0	29	0	0
T25	0	35	0	0
T26	0	32	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0
T35	0	11	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1978	0	0
T17	351374	16	0	0
T18	177890	14	0	0
T19	0	48	0	0
T20	0	51	0	0
T21	0	24	0	0
T22	0	20	0	0
T23	0	16	0	0
T24	0	32	0	0
T25	0	32	0	0
T26	0	31	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1883	0	0
T17	351374	13	0	0
T18	177890	8	0	0
T19	0	39	0	0
T20	0	36	0	0
T21	0	24	0	0
T22	0	65	0	0
T23	0	8	0	0
T24	0	21	0	0
T25	0	34	0	0
T26	0	43	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1985	0	0
T17	351374	24	0	0
T18	177890	14	0	0
T19	0	26	0	0
T20	0	29	0	0
T21	0	21	0	0
T22	0	49	0	0
T23	0	17	0	0
T24	0	39	0	0
T25	0	48	0	0
T26	0	39	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1663	0	0
T17	351374	13	0	0
T18	177890	12	0	0
T19	0	48	0	0
T20	0	51	0	0
T21	0	24	0	0
T22	0	47	0	0
T23	0	3	0	0
T24	0	32	0	0
T25	0	39	0	0
T26	0	33	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1903	0	0
T17	351374	24	0	0
T18	177890	1	0	0
T19	0	48	0	0
T20	0	54	0	0
T21	0	28	0	0
T22	0	54	0	0
T23	0	11	0	0
T24	0	25	0	0
T25	0	25	0	0
T26	0	37	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1881	0	0
T17	351374	19	0	0
T18	177890	9	0	0
T19	0	47	0	0
T20	0	34	0	0
T21	0	25	0	0
T22	0	34	0	0
T23	0	16	0	0
T24	0	20	0	0
T25	0	24	0	0
T26	0	35	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1707	0	0
T17	351374	27	0	0
T18	177890	9	0	0
T19	0	54	0	0
T20	0	43	0	0
T21	0	19	0	0
T22	0	37	0	0
T23	0	6	0	0
T24	0	30	0	0
T25	0	38	0	0
T26	0	32	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1677	0	0
T17	351374	11	0	0
T18	177890	14	0	0
T19	0	31	0	0
T20	0	33	0	0
T21	0	32	0	0
T22	0	46	0	0
T23	0	5	0	0
T24	0	33	0	0
T25	0	45	0	0
T26	0	35	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1936	0	0
T17	351374	15	0	0
T18	177890	11	0	0
T19	0	48	0	0
T20	0	37	0	0
T21	0	26	0	0
T22	0	46	0	0
T23	0	13	0	0
T24	0	14	0	0
T25	0	37	0	0
T26	0	34	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1724	0	0
T17	351374	11	0	0
T18	177890	7	0	0
T19	0	53	0	0
T20	0	48	0	0
T21	0	12	0	0
T22	0	26	0	0
T23	0	4	0	0
T24	0	39	0	0
T25	0	21	0	0
T26	0	46	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1984	0	0
T17	351374	22	0	0
T18	177890	13	0	0
T19	0	46	0	0
T20	0	50	0	0
T21	0	18	0	0
T22	0	52	0	0
T23	0	13	0	0
T24	0	16	0	0
T25	0	27	0	0
T26	0	27	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1993	0	0
T17	351374	21	0	0
T18	177890	18	0	0
T19	0	34	0	0
T20	0	52	0	0
T21	0	19	0	0
T22	0	37	0	0
T23	0	8	0	0
T24	0	19	0	0
T25	0	47	0	0
T26	0	41	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1770	0	0
T17	351374	8	0	0
T18	177890	1	0	0
T19	0	45	0	0
T20	0	41	0	0
T21	0	19	0	0
T22	0	57	0	0
T23	0	21	0	0
T24	0	16	0	0
T25	0	33	0	0
T26	0	45	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1531	0	0
T17	351374	24	0	0
T18	177890	6	0	0
T19	0	37	0	0
T20	0	46	0	0
T21	0	32	0	0
T22	0	45	0	0
T23	0	13	0	0
T24	0	29	0	0
T25	0	38	0	0
T26	0	43	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1323	0	0
T17	351374	21	0	0
T18	177890	9	0	0
T19	0	40	0	0
T20	0	38	0	0
T21	0	23	0	0
T22	0	38	0	0
T23	0	13	0	0
T24	0	22	0	0
T25	0	23	0	0
T26	0	31	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1746	0	0
T17	351374	13	0	0
T18	177890	7	0	0
T19	0	45	0	0
T20	0	47	0	0
T21	0	24	0	0
T22	0	45	0	0
T23	0	8	0	0
T24	0	28	0	0
T25	0	36	0	0
T26	0	42	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1430	0	0
T17	351374	22	0	0
T18	177890	8	0	0
T19	0	41	0	0
T20	0	41	0	0
T21	0	20	0	0
T22	0	34	0	0
T23	0	5	0	0
T24	0	20	0	0
T25	0	41	0	0
T26	0	38	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1458	0	0
T17	351374	18	0	0
T18	177890	5	0	0
T19	0	34	0	0
T20	0	46	0	0
T21	0	24	0	0
T22	0	36	0	0
T23	0	9	0	0
T24	0	21	0	0
T25	0	43	0	0
T26	0	22	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1348	0	0
T17	351374	19	0	0
T18	177890	3	0	0
T19	0	32	0	0
T20	0	38	0	0
T21	0	8	0	0
T22	0	40	0	0
T23	0	16	0	0
T24	0	30	0	0
T25	0	39	0	0
T26	0	34	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1529	0	0
T17	351374	27	0	0
T18	177890	19	0	0
T19	0	34	0	0
T20	0	37	0	0
T21	0	15	0	0
T22	0	44	0	0
T23	0	24	0	0
T24	0	31	0	0
T25	0	46	0	0
T26	0	25	0	0
T27	176095	0	0	0
T28	312414	0	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1866	0	0
T17	351374	15	0	0
T18	177890	28	0	0
T19	0	40	0	0
T20	0	48	0	0
T21	0	27	0	0
T22	0	60	0	0
T23	0	43	0	0
T27	176095	0	0	0
T28	312414	22	0	0
T29	124009	0	0	0
T30	161833	0	0	0
T31	436132	0	0	0
T32	132018	0	0	0
T33	131483	0	0	0
T34	105125	0	0	0
T36	0	16	0	0
T37	0	29	0	0