Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1170392	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1146103

1

T1

2096

T2

1399

T3

1128

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2027554	1			T1	3992		T2	2499		T3	2090
values[0x0]	143972	1			T1	120		T2	169		T3	134
values[0x1]	144969	1			T1	118		T2	150		T3	114

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	937411	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1379084

1

T1

2533

T2

1674

T3

1366

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6850	1			T1	14		T4	2		T6	2
valid_sources[0x01]	9512	1			T1	17		T4	8		T6	1
valid_sources[0x02]	7308	1			T1	7		T3	14		T4	42
valid_sources[0x03]	7281	1			T1	35		T4	4		T6	3
valid_sources[0x04]	10246	1			T1	11		T3	17		T4	2
valid_sources[0x05]	8200	1			T1	22		T4	6		T6	2
valid_sources[0x06]	10958	1			T1	16		T4	7		T6	3
valid_sources[0x07]	6798	1			T1	24		T3	2		T4	2
valid_sources[0x08]	7150	1			T1	15		T3	49		T4	3
valid_sources[0x09]	7262	1			T1	14		T3	2		T4	3
valid_sources[0x0a]	11666	1			T1	19		T4	6		T7	3
valid_sources[0x0b]	7506	1			T1	17		T6	1		T7	6
valid_sources[0x0c]	8854	1			T1	22		T5	3		T6	1
valid_sources[0x0d]	9509	1			T1	14		T6	2		T7	4
valid_sources[0x0e]	7023	1			T1	10		T3	25		T4	2
valid_sources[0x0f]	12320	1			T1	28		T4	4		T6	2
valid_sources[0x10]	15940	1			T1	20		T3	3		T4	16
valid_sources[0x11]	11585	1			T1	18		T3	38		T4	1
valid_sources[0x12]	15246	1			T1	15		T2	1		T4	4
valid_sources[0x13]	6954	1			T1	10		T4	7		T6	6
valid_sources[0x14]	11246	1			T1	14		T3	10		T4	4
valid_sources[0x15]	7768	1			T1	28		T3	34		T4	3
valid_sources[0x16]	7059	1			T1	11		T2	1		T3	18
valid_sources[0x17]	7143	1			T1	9		T4	5		T6	2
valid_sources[0x18]	11503	1			T1	21		T4	31		T6	3
valid_sources[0x19]	7984	1			T1	22		T3	5		T4	5
valid_sources[0x1a]	15733	1			T1	6		T3	20		T4	2
valid_sources[0x1b]	9255	1			T1	20		T4	2		T6	2
valid_sources[0x1c]	14281	1			T1	8		T3	21		T4	1
valid_sources[0x1d]	6967	1			T1	16		T2	1		T3	1
valid_sources[0x1e]	7129	1			T1	9		T2	1		T4	4
valid_sources[0x1f]	11231	1			T1	15		T4	4		T6	2
valid_sources[0x20]	8537	1			T1	17		T4	59		T6	1
valid_sources[0x21]	8605	1			T1	22		T3	58		T4	1
valid_sources[0x22]	11754	1			T1	13		T2	1		T3	20
valid_sources[0x23]	11173	1			T1	24		T2	1		T3	14
valid_sources[0x24]	8004	1			T1	15		T4	7		T6	2
valid_sources[0x25]	8883	1			T1	12		T3	9		T4	8
valid_sources[0x26]	8031	1			T1	22		T4	2		T6	6
valid_sources[0x27]	7058	1			T1	17		T3	72		T4	2
valid_sources[0x28]	8862	1			T1	15		T4	5		T7	3
valid_sources[0x29]	7086	1			T1	19		T3	8		T4	4
valid_sources[0x2a]	7979	1			T1	17		T4	20		T6	3
valid_sources[0x2b]	12730	1			T1	17		T3	40		T4	1
valid_sources[0x2c]	7062	1			T1	13		T3	1		T4	4
valid_sources[0x2d]	7175	1			T1	22		T3	10		T4	2
valid_sources[0x2e]	8044	1			T1	11		T2	1		T3	32
valid_sources[0x2f]	6933	1			T1	16		T4	5		T7	9
valid_sources[0x30]	7108	1			T1	13		T4	4		T6	2
valid_sources[0x31]	7858	1			T1	10		T4	5		T6	5
valid_sources[0x32]	8123	1			T1	7		T4	5		T6	1
valid_sources[0x33]	9789	1			T1	17		T3	16		T6	1
valid_sources[0x34]	11059	1			T1	11		T4	2		T6	1
valid_sources[0x35]	7960	1			T1	15		T4	6		T6	1
valid_sources[0x36]	6747	1			T1	22		T3	4		T4	4
valid_sources[0x37]	11601	1			T1	17		T4	2		T6	3
valid_sources[0x38]	7985	1			T1	23		T3	4		T4	2
valid_sources[0x39]	9684	1			T1	23		T4	2		T6	2
valid_sources[0x3a]	14125	1			T1	33		T4	25		T7	6
valid_sources[0x3b]	6866	1			T1	17		T3	26		T4	1
valid_sources[0x3c]	6922	1			T1	12		T4	3		T6	5
valid_sources[0x3d]	8273	1			T1	19		T2	2		T4	5
valid_sources[0x3e]	6857	1			T1	10		T4	3		T6	2
valid_sources[0x3f]	16100	1			T1	26		T3	1		T4	3
valid_sources[0x40]	8763	1			T1	17		T2	1		T4	2
valid_sources[0x41]	15089	1			T1	10		T3	49		T4	1
valid_sources[0x42]	12099	1			T1	11		T3	38		T4	7
valid_sources[0x43]	8465	1			T1	19		T4	1		T6	4
valid_sources[0x44]	7212	1			T1	17		T3	27		T4	3
valid_sources[0x45]	11474	1			T1	12		T3	9		T4	3
valid_sources[0x46]	8008	1			T1	19		T4	32		T6	4
valid_sources[0x47]	7316	1			T1	19		T4	4		T6	2
valid_sources[0x48]	8049	1			T1	12		T4	2		T7	6
valid_sources[0x49]	11046	1			T1	13		T4	7		T6	2
valid_sources[0x4a]	7568	1			T1	23		T4	2		T6	2
valid_sources[0x4b]	7098	1			T1	13		T3	21		T4	11
valid_sources[0x4c]	16803	1			T1	15		T4	8		T6	1
valid_sources[0x4d]	9923	1			T1	7		T3	4		T4	9
valid_sources[0x4e]	8333	1			T1	10		T4	3		T6	5
valid_sources[0x4f]	8002	1			T1	18		T4	4		T6	2
valid_sources[0x50]	7317	1			T1	18		T4	2		T6	6
valid_sources[0x51]	7077	1			T1	20		T4	1		T6	7
valid_sources[0x52]	18213	1			T1	11		T3	13		T4	1
valid_sources[0x53]	9514	1			T1	31		T2	2784		T3	18
valid_sources[0x54]	7445	1			T1	15		T3	22		T4	1
valid_sources[0x55]	7397	1			T1	12		T4	4		T6	3
valid_sources[0x56]	11591	1			T1	20		T4	24		T7	6
valid_sources[0x57]	6956	1			T1	12		T3	10		T4	3
valid_sources[0x58]	12496	1			T1	27		T5	2		T6	6
valid_sources[0x59]	9441	1			T1	19		T4	7		T6	1
valid_sources[0x5a]	11470	1			T1	18		T3	6		T4	8
valid_sources[0x5b]	11730	1			T1	14		T4	3		T6	7
valid_sources[0x5c]	7233	1			T1	16		T4	4		T5	1
valid_sources[0x5d]	7773	1			T1	17		T4	3		T6	1
valid_sources[0x5e]	7024	1			T1	23		T3	14		T4	3
valid_sources[0x5f]	9586	1			T1	12		T2	1		T4	3
valid_sources[0x60]	7968	1			T1	15		T4	4		T6	1
valid_sources[0x61]	16718	1			T1	11		T4	1		T6	4
valid_sources[0x62]	8405	1			T1	16		T3	24		T4	10
valid_sources[0x63]	7123	1			T1	16		T3	13		T4	4
valid_sources[0x64]	11144	1			T1	12		T2	2		T4	1
valid_sources[0x65]	7082	1			T1	19		T3	12		T4	3
valid_sources[0x66]	9698	1			T1	15		T2	1		T4	1
valid_sources[0x67]	8407	1			T1	24		T4	13		T6	5
valid_sources[0x68]	12081	1			T1	19		T3	20		T4	89
valid_sources[0x69]	6749	1			T1	8		T4	2		T6	1
valid_sources[0x6a]	13949	1			T1	6		T3	135		T4	3
valid_sources[0x6b]	8481	1			T1	12		T4	7		T7	9
valid_sources[0x6c]	7583	1			T1	16		T4	3		T7	3
valid_sources[0x6d]	7062	1			T1	20		T4	4		T6	3
valid_sources[0x6e]	7022	1			T1	11		T3	2		T4	10
valid_sources[0x6f]	7887	1			T1	12		T2	1		T3	25
valid_sources[0x70]	10014	1			T1	17		T4	1		T6	4
valid_sources[0x71]	8232	1			T1	18		T2	1		T4	1
valid_sources[0x72]	8024	1			T1	10		T3	24		T7	3
valid_sources[0x73]	9051	1			T1	19		T3	14		T4	1
valid_sources[0x74]	6699	1			T1	24		T4	10		T6	4
valid_sources[0x75]	7324	1			T1	11		T3	27		T4	2
valid_sources[0x76]	8424	1			T1	22		T4	3		T6	1
valid_sources[0x77]	7108	1			T1	6		T4	4		T6	2
valid_sources[0x78]	8294	1			T1	25		T4	4		T6	3
valid_sources[0x79]	7021	1			T1	11		T4	3		T6	6
valid_sources[0x7a]	8994	1			T1	16		T4	3		T6	1
valid_sources[0x7b]	7269	1			T1	27		T4	4		T6	2
valid_sources[0x7c]	7227	1			T1	10		T3	25		T4	2
valid_sources[0x7d]	7098	1			T1	12		T4	4		T6	2
valid_sources[0x7e]	7024	1			T1	30		T4	3		T7	5
valid_sources[0x7f]	11472	1			T1	20		T4	3		T6	3
valid_sources[0x80]	7197	1			T1	21		T4	3		T6	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1010652

1

T1

2015

T2

1264

T3

1037

values[0x0]

all_enables

biggest_size

78552

1

T1

50

T2

82

T3

65

values[0x1]

all_enables

biggest_size

56899

1

T1

31

T2

53

T3

26