Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28833	1			T1	7		T2	11		T3	5
auto[PWRUP]	113	1			T7	1		T13	1		T49	1
auto[ONEST_0]	67	1			T49	1		T50	1		T52	1
auto[ONEST_021]	19	1			T6	1		T51	1		T54	1
auto[ONEST_1]	70	1			T6	1		T49	1		T50	3
auto[ONEST_DONE]	3	1			T233	1		T234	1		T235	1
auto[LP_0]	128	1			T13	1		T51	3		T49	2
auto[LP_021]	29	1			T13	1		T51	1		T49	1
auto[LP_1]	138	1			T6	1		T49	2		T52	1
auto[LP_EVAL]	68	1			T49	1		T50	1		T52	1
auto[LP_SLP]	457	1			T6	3		T7	2		T13	4
auto[LP_PWRUP]	24	1			T50	2		T52	1		T54	2
auto[NP_0]	158	1			T6	1		T13	1		T51	1
auto[NP_021]	25	1			T6	1		T96	1		T80	1
auto[NP_1]	161	1			T6	1		T13	2		T51	4
auto[NP_EVAL]	36	1			T6	1		T13	1		T49	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

2

1

T236

1

T237

1

-

-

min

28273

1

T1

7

T2

11

T3

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28279	1			T1	7		T2	11		T3	5
pow[0x1]	7	1			T238	2		T239	1		T240	1
pow[0x2]	14	1			T96	1		T85	1		T241	1
pow[0x3]	35	1			T13	1		T49	1		T50	2
pow[0x4]	67	1			T6	1		T49	1		T50	1
pow[0x5]	128	1			T6	1		T13	1		T51	1
pow[0x6]	240	1			T6	2		T13	1		T51	2
pow[0x7]	530	1			T6	5		T13	8		T51	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

188

1

T13

3

T49

2

T50

2

min

27848

1

T1

7

T2

11

T3

5

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27848	1			T1	7		T2	11		T3	5
pow[0x3]	1	1			T240	1		-	-		-	-
pow[0x4]	1	1			T242	1		-	-		-	-
pow[0x6]	1	1			T243	1		-	-		-	-
pow[0x7]	5	1			T52	1		T38	1		T244	1
pow[0x8]	9	1			T91	1		T245	1		T246	1
pow[0x9]	7	1			T54	1		T241	1		T247	1
pow[0xa]	13	1			T49	1		T140	1		T248	1
pow[0xb]	39	1			T50	1		T52	1		T96	2
pow[0xc]	70	1			T6	1		T13	4		T51	1
pow[0xd]	160	1			T13	1		T49	4		T50	1
pow[0xe]	289	1			T6	7		T51	2		T49	7
pow[0xf]	543	1			T6	6		T7	1		T13	5