Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2244	1			T6	14		T7	15		T10	3
auto[PWRUP]	133	1			T7	1		T13	3		T49	1
auto[ONEST_0]	88	1			T7	1		T13	1		T51	1
auto[ONEST_021]	16	1			T39	1		T383	1		T53	1
auto[ONEST_1]	79	1			T13	4		T38	1		T96	1
auto[ONEST_DONE]	6	1			T326	1		T239	1		T235	1
auto[LP_0]	120	1			T6	1		T51	2		T50	1
auto[LP_021]	35	1			T49	2		T96	2		T383	1
auto[LP_1]	164	1			T7	1		T13	5		T51	2
auto[LP_EVAL]	60	1			T7	2		T51	1		T49	1
auto[LP_SLP]	565	1			T6	9		T7	2		T13	8
auto[LP_PWRUP]	35	1			T51	1		T50	1		T85	1
auto[NP_0]	236	1			T6	1		T7	2		T13	2
auto[NP_021]	42	1			T51	2		T36	1		T38	1
auto[NP_1]	239	1			T6	4		T7	4		T13	1
auto[NP_EVAL]	34	1			T15	1		T241	2		T292	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T85

1

T384

1

T385

1

min

1964

1

T6

9

T7

17

T10

3

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1981	1			T6	9		T7	18		T10	3
pow[0x1]	15	1			T7	1		T386	2		T45	1
pow[0x2]	17	1			T53	1		T17	1		T238	1
pow[0x3]	25	1			T49	1		T38	1		T85	1
pow[0x4]	74	1			T6	1		T13	1		T49	1
pow[0x5]	160	1			T6	3		T7	1		T13	3
pow[0x6]	244	1			T6	2		T7	1		T13	3
pow[0x7]	524	1			T6	5		T7	2		T13	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

200

1

T13

3

T51

2

T49

3

min

1348

1

T6

1

T7

16

T10

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1357	1			T6	1		T7	16		T10	3
pow[0x1]	12	1			T7	3		T15	2		T286	1
pow[0x2]	24	1			T36	2		T16	1		T38	2
pow[0x3]	51	1			T16	2		T38	1		T39	1
pow[0x4]	50	1			T15	3		T36	2		T16	1
pow[0x5]	1	1			T384	1		-	-		-	-
pow[0x6]	1	1			T20	1		-	-		-	-
pow[0x7]	3	1			T387	1		T264	1		T388	1
pow[0x8]	3	1			T389	1		T245	1		T390	1
pow[0x9]	3	1			T96	1		T383	1		T336	1
pow[0xa]	14	1			T51	1		T238	3		T389	1
pow[0xb]	31	1			T49	1		T50	1		T54	1
pow[0xc]	86	1			T6	2		T13	1		T51	2
pow[0xd]	160	1			T6	2		T7	3		T13	5
pow[0xe]	313	1			T6	3		T13	4		T51	4
pow[0xf]	612	1			T6	8		T7	1		T13	9