Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2751	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2673	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2561	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2473	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2648	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2774	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2649	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2515	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2656	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2533	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2626	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2627	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2825	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2488	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2620	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2715	0	0
adc_en_ctl_rd_A	2147483647	2390	0	0
adc_fsm_rst_rd_A	2147483647	2242	0	0
adc_intr_ctl_rd_A	2147483647	3049	0	0
adc_lp_sample_ctl_rd_A	2147483647	2534	0	0
adc_pd_ctl_rd_A	2147483647	2537	0	0
adc_sample_ctl_rd_A	2147483647	2134	0	0
adc_wakeup_ctl_rd_A	2147483647	2134	0	0
intr_enable_rd_A	2147483647	3048	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2751	0	0
T15	452911	35	0	0
T16	0	20	0	0
T17	0	17	0	0
T18	0	18	0	0
T19	0	26	0	0
T20	0	8	0	0
T21	0	32	0	0
T22	0	18	0	0
T23	0	37	0	0
T24	0	13	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2673	0	0
T15	452911	22	0	0
T16	0	32	0	0
T17	0	22	0	0
T18	0	7	0	0
T19	0	21	0	0
T20	0	3	0	0
T21	0	47	0	0
T22	0	15	0	0
T23	0	35	0	0
T24	0	21	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2561	0	0
T15	452911	33	0	0
T16	0	20	0	0
T17	0	24	0	0
T18	0	11	0	0
T19	0	18	0	0
T21	0	26	0	0
T22	0	18	0	0
T23	0	34	0	0
T24	0	15	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0
T34	0	19	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2473	0	0
T15	452911	39	0	0
T16	0	16	0	0
T17	0	17	0	0
T18	0	16	0	0
T19	0	24	0	0
T20	0	7	0	0
T21	0	24	0	0
T22	0	16	0	0
T23	0	30	0	0
T24	0	10	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2648	0	0
T15	452911	24	0	0
T16	0	20	0	0
T17	0	22	0	0
T18	0	11	0	0
T19	0	16	0	0
T20	0	14	0	0
T21	0	37	0	0
T22	0	23	0	0
T23	0	42	0	0
T24	0	14	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2774	0	0
T15	452911	32	0	0
T16	0	18	0	0
T17	0	24	0	0
T18	0	18	0	0
T19	0	15	0	0
T20	0	5	0	0
T21	0	32	0	0
T22	0	19	0	0
T23	0	32	0	0
T24	0	12	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2649	0	0
T15	452911	45	0	0
T16	0	24	0	0
T17	0	16	0	0
T18	0	20	0	0
T19	0	21	0	0
T20	0	4	0	0
T21	0	40	0	0
T22	0	22	0	0
T23	0	45	0	0
T24	0	13	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2515	0	0
T15	452911	33	0	0
T16	0	19	0	0
T17	0	17	0	0
T18	0	19	0	0
T19	0	23	0	0
T20	0	3	0	0
T21	0	42	0	0
T22	0	16	0	0
T23	0	40	0	0
T24	0	18	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2656	0	0
T15	452911	41	0	0
T16	0	15	0	0
T17	0	16	0	0
T18	0	18	0	0
T19	0	22	0	0
T21	0	41	0	0
T22	0	21	0	0
T23	0	40	0	0
T24	0	10	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0
T34	0	29	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2533	0	0
T15	452911	32	0	0
T16	0	19	0	0
T17	0	19	0	0
T18	0	14	0	0
T19	0	24	0	0
T20	0	4	0	0
T21	0	29	0	0
T22	0	15	0	0
T23	0	40	0	0
T24	0	7	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2626	0	0
T15	452911	38	0	0
T16	0	26	0	0
T17	0	17	0	0
T18	0	19	0	0
T19	0	9	0	0
T20	0	1	0	0
T21	0	31	0	0
T22	0	16	0	0
T23	0	36	0	0
T24	0	27	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2627	0	0
T15	452911	37	0	0
T16	0	10	0	0
T17	0	17	0	0
T18	0	24	0	0
T19	0	25	0	0
T20	0	8	0	0
T21	0	48	0	0
T22	0	14	0	0
T23	0	27	0	0
T24	0	24	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2825	0	0
T15	452911	44	0	0
T16	0	27	0	0
T17	0	25	0	0
T18	0	26	0	0
T19	0	14	0	0
T20	0	20	0	0
T21	0	49	0	0
T22	0	15	0	0
T23	0	27	0	0
T24	0	14	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2488	0	0
T15	452911	43	0	0
T16	0	16	0	0
T17	0	14	0	0
T18	0	28	0	0
T19	0	22	0	0
T20	0	13	0	0
T21	0	61	0	0
T22	0	12	0	0
T23	0	35	0	0
T24	0	24	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2620	0	0
T15	452911	31	0	0
T16	0	14	0	0
T17	0	38	0	0
T18	0	21	0	0
T19	0	26	0	0
T20	0	16	0	0
T21	0	44	0	0
T22	0	13	0	0
T23	0	24	0	0
T24	0	10	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2715	0	0
T15	452911	46	0	0
T16	0	28	0	0
T17	0	19	0	0
T18	0	20	0	0
T19	0	11	0	0
T21	0	31	0	0
T22	0	18	0	0
T23	0	34	0	0
T24	0	25	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0
T34	0	17	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2390	0	0
T15	452911	37	0	0
T16	0	26	0	0
T17	0	17	0	0
T18	0	16	0	0
T19	0	6	0	0
T20	0	3	0	0
T21	0	50	0	0
T22	0	18	0	0
T23	0	32	0	0
T24	0	22	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2242	0	0
T15	452911	40	0	0
T16	0	19	0	0
T17	0	30	0	0
T18	0	8	0	0
T19	0	27	0	0
T20	0	6	0	0
T21	0	34	0	0
T22	0	27	0	0
T23	0	50	0	0
T24	0	12	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3049	0	0
T15	452911	34	0	0
T16	0	16	0	0
T17	0	21	0	0
T18	0	29	0	0
T19	0	13	0	0
T20	0	10	0	0
T21	0	41	0	0
T22	0	19	0	0
T23	0	41	0	0
T24	0	20	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2534	0	0
T15	452911	40	0	0
T16	0	10	0	0
T17	0	18	0	0
T18	0	17	0	0
T19	0	8	0	0
T20	0	2	0	0
T21	0	25	0	0
T22	0	20	0	0
T23	0	50	0	0
T24	0	14	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2537	0	0
T15	452911	36	0	0
T16	0	18	0	0
T17	0	21	0	0
T18	0	15	0	0
T19	0	26	0	0
T20	0	14	0	0
T21	0	36	0	0
T22	0	30	0	0
T23	0	46	0	0
T24	0	24	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2134	0	0
T15	452911	35	0	0
T16	0	19	0	0
T17	0	26	0	0
T18	0	11	0	0
T19	0	9	0	0
T20	0	15	0	0
T21	0	28	0	0
T22	0	18	0	0
T23	0	42	0	0
T24	0	20	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2134	0	0
T15	452911	33	0	0
T16	0	8	0	0
T17	0	28	0	0
T18	0	5	0	0
T19	0	23	0	0
T20	0	14	0	0
T21	0	28	0	0
T22	0	28	0	0
T23	0	32	0	0
T24	0	19	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
T30	803376	0	0	0
T31	696307	0	0	0
T32	332680	0	0	0
T33	147289	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3048	0	0
T15	452911	60	0	0
T16	0	24	0	0
T17	0	12	0	0
T18	0	25	0	0
T19	0	32	0	0
T20	0	2	0	0
T21	0	51	0	0
T22	0	20	0	0
T23	0	52	0	0
T25	118310	0	0	0
T26	159710	0	0	0
T27	825881	0	0	0
T28	826490	0	0	0
T29	405201	0	0	0
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