Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1201790	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1176624

1

T1

32

T2

483

T3

482

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2082742	1			T3	860		T4	5		T13	1
values[0x0]	147160	1			T1	30		T2	601		T3	64
values[0x1]	148512	1			T1	28		T2	654		T3	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	963534	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1414880

1

T1

37

T2

585

T3

575

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7231	1			T1	3		T2	5		T13	1
valid_sources[0x01]	7808	1			T2	3		T3	5		T5	18
valid_sources[0x02]	12778	1			T2	7		T3	3		T5	20
valid_sources[0x03]	7608	1			T2	3		T3	3		T13	1
valid_sources[0x04]	7579	1			T2	3		T3	4		T5	17
valid_sources[0x05]	6958	1			T2	4		T3	8		T5	14
valid_sources[0x06]	9809	1			T2	8		T3	4		T4	1
valid_sources[0x07]	19934	1			T2	10		T3	3		T5	20
valid_sources[0x08]	6995	1			T2	6		T3	4		T4	1
valid_sources[0x09]	7338	1			T2	2		T3	3		T5	32
valid_sources[0x0a]	7394	1			T1	2		T2	3		T3	5
valid_sources[0x0b]	7223	1			T2	3		T3	1		T4	1
valid_sources[0x0c]	7333	1			T2	5		T3	6		T5	14
valid_sources[0x0d]	12498	1			T2	4		T3	1		T5	11
valid_sources[0x0e]	8362	1			T2	3		T3	3		T5	14
valid_sources[0x0f]	7064	1			T2	11		T3	3		T4	1
valid_sources[0x10]	7660	1			T2	7		T3	5		T13	1
valid_sources[0x11]	10045	1			T2	7		T3	6		T5	18
valid_sources[0x12]	7688	1			T2	5		T3	8		T5	13
valid_sources[0x13]	9035	1			T3	3		T5	11		T6	4
valid_sources[0x14]	7545	1			T2	10		T3	6		T4	1
valid_sources[0x15]	8395	1			T2	4		T3	1		T5	25
valid_sources[0x16]	11630	1			T3	5		T5	15		T6	1
valid_sources[0x17]	10336	1			T2	6		T3	2		T5	13
valid_sources[0x18]	20075	1			T2	9		T3	6		T5	12
valid_sources[0x19]	12356	1			T2	3		T3	3		T5	23
valid_sources[0x1a]	7171	1			T2	5		T3	6		T5	16
valid_sources[0x1b]	15026	1			T2	2		T3	1		T5	25
valid_sources[0x1c]	8308	1			T2	3		T3	2		T5	18
valid_sources[0x1d]	12567	1			T2	5		T3	3		T5	19
valid_sources[0x1e]	7628	1			T3	2		T5	11		T7	8
valid_sources[0x1f]	7979	1			T2	5		T3	6		T5	13
valid_sources[0x20]	8125	1			T1	2		T2	3		T3	7
valid_sources[0x21]	9063	1			T1	11		T2	4		T3	1
valid_sources[0x22]	8183	1			T2	8		T3	3		T5	12
valid_sources[0x23]	7059	1			T2	5		T3	2		T5	14
valid_sources[0x24]	6650	1			T2	1		T3	3		T5	15
valid_sources[0x25]	8267	1			T2	3		T3	3		T4	3
valid_sources[0x26]	7209	1			T2	4		T3	7		T5	13
valid_sources[0x27]	8144	1			T2	5		T5	17		T7	9
valid_sources[0x28]	7364	1			T2	7		T3	4		T5	14
valid_sources[0x29]	7240	1			T2	6		T3	4		T5	19
valid_sources[0x2a]	7222	1			T2	6		T3	5		T5	16
valid_sources[0x2b]	7261	1			T1	1		T2	3		T3	1
valid_sources[0x2c]	7555	1			T2	9		T3	2		T5	19
valid_sources[0x2d]	6871	1			T1	5		T2	8		T3	3
valid_sources[0x2e]	8245	1			T2	3		T3	5		T5	26
valid_sources[0x2f]	8220	1			T2	3		T3	3		T5	14
valid_sources[0x30]	11133	1			T2	2		T3	7		T5	18
valid_sources[0x31]	7089	1			T2	3		T3	2		T5	13
valid_sources[0x32]	11997	1			T3	5		T5	24		T7	4
valid_sources[0x33]	7821	1			T2	4		T3	3		T5	18
valid_sources[0x34]	7188	1			T2	3		T5	15		T7	12
valid_sources[0x35]	7357	1			T2	3		T3	6		T5	16
valid_sources[0x36]	6919	1			T2	6		T3	4		T5	16
valid_sources[0x37]	12272	1			T1	6		T2	3		T3	2
valid_sources[0x38]	8512	1			T2	6		T3	5		T5	24
valid_sources[0x39]	16547	1			T2	3		T3	7		T5	21
valid_sources[0x3a]	7512	1			T2	7		T3	3		T5	26
valid_sources[0x3b]	14572	1			T2	2		T3	5		T13	1
valid_sources[0x3c]	8294	1			T2	11		T3	4		T5	22
valid_sources[0x3d]	12724	1			T2	4		T3	2		T5	22
valid_sources[0x3e]	12458	1			T2	6		T3	1		T5	21
valid_sources[0x3f]	7327	1			T2	2		T3	4		T5	22
valid_sources[0x40]	7047	1			T2	3		T3	4		T4	1
valid_sources[0x41]	12561	1			T2	6		T3	2		T5	29
valid_sources[0x42]	7629	1			T2	3		T3	1		T5	17
valid_sources[0x43]	7013	1			T2	2		T3	2		T5	13
valid_sources[0x44]	7893	1			T2	2		T3	7		T5	20
valid_sources[0x45]	7131	1			T2	10		T3	5		T5	18
valid_sources[0x46]	6966	1			T2	10		T3	6		T5	17
valid_sources[0x47]	19897	1			T2	4		T3	4		T5	34
valid_sources[0x48]	10251	1			T2	6		T3	5		T5	13
valid_sources[0x49]	6954	1			T2	5		T3	4		T5	21
valid_sources[0x4a]	7669	1			T2	3		T3	2		T5	14
valid_sources[0x4b]	8708	1			T2	5		T3	4		T4	2
valid_sources[0x4c]	11603	1			T2	2		T3	3		T4	1
valid_sources[0x4d]	11570	1			T2	3		T3	5		T5	20
valid_sources[0x4e]	7307	1			T1	7		T2	7		T3	6
valid_sources[0x4f]	11005	1			T2	7		T3	1		T5	15
valid_sources[0x50]	7091	1			T2	6		T3	5		T5	22
valid_sources[0x51]	12616	1			T2	4		T3	2		T5	18
valid_sources[0x52]	9092	1			T2	4		T3	3		T5	20
valid_sources[0x53]	7991	1			T2	6		T3	3		T5	18
valid_sources[0x54]	10747	1			T2	1		T3	2		T5	20
valid_sources[0x55]	6975	1			T2	3		T3	5		T5	22
valid_sources[0x56]	8303	1			T2	12		T3	10		T5	13
valid_sources[0x57]	12059	1			T2	5		T3	4		T5	15
valid_sources[0x58]	6983	1			T2	4		T3	6		T5	14
valid_sources[0x59]	12272	1			T2	2		T3	6		T5	11
valid_sources[0x5a]	7099	1			T2	4		T3	6		T5	7
valid_sources[0x5b]	14348	1			T2	3		T3	1		T4	1
valid_sources[0x5c]	9684	1			T2	3		T3	3		T5	15
valid_sources[0x5d]	8040	1			T2	2		T3	1		T5	10
valid_sources[0x5e]	10430	1			T2	4		T3	1		T5	18
valid_sources[0x5f]	6960	1			T2	4		T3	4		T5	6
valid_sources[0x60]	6997	1			T2	3		T3	3		T5	15
valid_sources[0x61]	7410	1			T2	3		T3	2		T5	16
valid_sources[0x62]	7350	1			T2	5		T3	5		T5	20
valid_sources[0x63]	8494	1			T2	6		T3	3		T5	19
valid_sources[0x64]	7050	1			T2	9		T3	6		T5	22
valid_sources[0x65]	7302	1			T2	10		T3	7		T5	16
valid_sources[0x66]	12597	1			T2	10		T3	4		T5	10
valid_sources[0x67]	13818	1			T2	1		T3	2		T5	18
valid_sources[0x68]	11849	1			T2	12		T3	2		T4	1
valid_sources[0x69]	7143	1			T2	8		T3	4		T5	14
valid_sources[0x6a]	10223	1			T2	4		T3	6		T4	1
valid_sources[0x6b]	7947	1			T2	5		T3	2		T13	1
valid_sources[0x6c]	18012	1			T2	2		T3	6		T5	12
valid_sources[0x6d]	7396	1			T2	5		T3	4		T5	10
valid_sources[0x6e]	12988	1			T2	2		T3	3		T4	1
valid_sources[0x6f]	7599	1			T2	7		T3	4		T5	17
valid_sources[0x70]	8262	1			T2	3		T3	3		T5	17
valid_sources[0x71]	10423	1			T1	1		T2	5		T3	4
valid_sources[0x72]	7306	1			T2	8		T3	8		T5	22
valid_sources[0x73]	7083	1			T2	7		T3	6		T4	1
valid_sources[0x74]	8695	1			T2	6		T3	5		T5	19
valid_sources[0x75]	17222	1			T2	7		T3	5		T4	1
valid_sources[0x76]	7363	1			T2	5		T5	16		T6	1
valid_sources[0x77]	7133	1			T2	1		T3	1		T4	1
valid_sources[0x78]	7446	1			T2	3		T3	6		T5	12
valid_sources[0x79]	8184	1			T3	5		T5	19		T7	14
valid_sources[0x7a]	6884	1			T2	5		T3	2		T5	24
valid_sources[0x7b]	12544	1			T2	12		T3	3		T5	20
valid_sources[0x7c]	11547	1			T2	3		T3	2		T13	1
valid_sources[0x7d]	8236	1			T2	10		T3	2		T4	1
valid_sources[0x7e]	10174	1			T2	5		T3	3		T5	10
valid_sources[0x7f]	7277	1			T2	8		T3	1		T4	1
valid_sources[0x80]	7606	1			T2	1		T3	4		T5	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1038729

1

T3

429

T4

4

T13

1

values[0x0]

all_enables

biggest_size

79939

1

T1

17

T2

273

T3

33

values[0x1]

all_enables

biggest_size

57956

1

T1

15

T2

210

T3

20