Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30480	1			T2	280		T3	9		T4	8
auto[PWRUP]	138	1			T2	2		T11	2		T48	2
auto[ONEST_0]	65	1			T2	1		T11	1		T48	1
auto[ONEST_021]	18	1			T67	1		T213	1		T51	1
auto[ONEST_1]	83	1			T2	2		T11	2		T48	1
auto[ONEST_DONE]	6	1			T227	1		T228	1		T229	1
auto[LP_0]	119	1			T2	2		T11	2		T48	4
auto[LP_021]	27	1			T11	1		T67	1		T213	2
auto[LP_1]	118	1			T2	1		T11	3		T48	1
auto[LP_EVAL]	75	1			T11	1		T48	2		T67	1
auto[LP_SLP]	533	1			T2	9		T11	3		T48	7
auto[LP_PWRUP]	22	1			T11	1		T48	1		T68	1
auto[NP_0]	141	1			T2	1		T11	4		T48	1
auto[NP_021]	33	1			T11	2		T51	1		T14	1
auto[NP_1]	152	1			T2	1		T11	4		T48	1
auto[NP_EVAL]	44	1			T48	1		T46	1		T51	5

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T183

1

T64

1

T230

2

min

29951

1

T2

268

T3

9

T4

8

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29956	1			T2	268		T3	9		T4	8
pow[0x1]	10	1			T231	1		T232	1		T233	1
pow[0x2]	17	1			T213	1		T51	1		T234	1
pow[0x3]	33	1			T11	1		T67	1		T112	1
pow[0x4]	64	1			T2	2		T11	1		T68	1
pow[0x5]	110	1			T2	2		T11	2		T112	1
pow[0x6]	261	1			T2	7		T11	6		T48	4
pow[0x7]	550	1			T2	8		T11	10		T48	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

210

1

T2

2

T11

3

T48

3

min

29462

1

T2

260

T3

9

T4

8

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29462	1			T2	260		T3	9		T4	8
pow[0x3]	1	1			T235	1		-	-		-	-
pow[0x5]	1	1			T51	1		-	-		-	-
pow[0x8]	4	1			T228	1		T236	1		T237	1
pow[0x9]	12	1			T227	1		T69	1		T236	1
pow[0xa]	18	1			T48	1		T112	1		T51	1
pow[0xb]	32	1			T48	1		T51	3		T228	1
pow[0xc]	78	1			T2	1		T48	2		T68	4
pow[0xd]	150	1			T2	4		T11	1		T48	2
pow[0xe]	294	1			T2	9		T11	2		T48	3
pow[0xf]	580	1			T2	8		T11	11		T48	4