Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2276	1			T2	16		T5	3		T11	16
auto[PWRUP]	142	1			T2	2		T11	1		T48	1
auto[ONEST_0]	77	1			T2	2		T48	3		T67	3
auto[ONEST_021]	18	1			T11	1		T46	1		T51	1
auto[ONEST_1]	80	1			T11	2		T48	1		T67	1
auto[ONEST_DONE]	6	1			T48	1		T68	1		T227	1
auto[LP_0]	131	1			T2	2		T11	2		T48	2
auto[LP_021]	30	1			T48	1		T112	1		T51	1
auto[LP_1]	161	1			T2	1		T48	2		T68	2
auto[LP_EVAL]	74	1			T2	1		T11	1		T48	1
auto[LP_SLP]	505	1			T2	7		T11	11		T48	7
auto[LP_PWRUP]	34	1			T11	1		T48	1		T46	1
auto[NP_0]	229	1			T2	1		T11	1		T48	4
auto[NP_021]	45	1			T46	1		T51	3		T69	2
auto[NP_1]	242	1			T2	5		T48	2		T67	3
auto[NP_EVAL]	31	1			T11	1		T14	1		T15	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T227

1

T362

1

T230

1

min

1948

1

T2

8

T5

3

T11

14

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1966	1			T2	8		T5	3		T11	14
pow[0x1]	18	1			T2	1		T67	1		T69	1
pow[0x2]	17	1			T67	1		T46	2		T213	1
pow[0x3]	23	1			T11	1		T112	1		T46	2
pow[0x4]	69	1			T2	1		T67	1		T213	1
pow[0x5]	126	1			T2	2		T11	1		T48	1
pow[0x6]	246	1			T2	5		T11	3		T48	6
pow[0x7]	562	1			T2	10		T11	9		T48	10

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

193

1

T2

1

T11

3

T48

3

min

1311

1

T2

2

T5

3

T11

1

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1316	1			T2	2		T5	3		T11	1
pow[0x1]	11	1			T47	1		T130	1		T298	3
pow[0x2]	30	1			T47	1		T51	2		T15	1
pow[0x3]	37	1			T45	1		T46	1		T51	1
pow[0x4]	79	1			T51	1		T32	2		T15	2
pow[0x5]	2	1			T11	1		T231	1		-	-
pow[0x8]	4	1			T357	1		T121	1		T363	1
pow[0x9]	9	1			T48	1		T227	1		T14	1
pow[0xa]	26	1			T213	1		T51	2		T69	1
pow[0xb]	44	1			T2	1		T11	2		T48	1
pow[0xc]	79	1			T11	1		T68	1		T112	2
pow[0xd]	154	1			T2	2		T11	2		T48	5
pow[0xe]	291	1			T2	3		T11	6		T48	7
pow[0xf]	600	1			T2	6		T11	8		T48	7