Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T12
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T12
0	1	Covered	T3,T5,T12
1	0	Covered	T3,T5,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T49
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T49
0	1	Covered	T3,T5,T49
1	0	Covered	T3,T5,T49

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T12
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T12
0	1	Covered	T3,T5,T12
1	0	Covered	T3,T5,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T3,T12,T49
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T49
0	1	Covered	T3,T12,T49
1	0	Covered	T3,T12,T49

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T5,T12,T40
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T12,T40
0	1	Covered	T5,T12,T40
1	0	Covered	T5,T12,T40

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T12
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T12
0	1	Covered	T3,T5,T12
1	0	Covered	T3,T5,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T49,T36,T40
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T5,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T12
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T12
0	1	Covered	T3,T5,T12
1	0	Covered	T3,T5,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T3,T49,T36
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T49,T36
0	1	Covered	T3,T49,T36
1	0	Covered	T3,T49,T36

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T12
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T12
0	1	Covered	T3,T5,T12
1	0	Covered	T3,T5,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T3,T12,T49
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T49
0	1	Covered	T3,T12,T49
1	0	Covered	T3,T12,T49

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T5,T12,T40
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T12,T40
0	1	Covered	T5,T12,T40
1	0	Covered	T5,T12,T40

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T12
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T12
0	1	Covered	T3,T5,T12
1	0	Covered	T3,T5,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T49,T36,T40
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T7,T8
1	1	0	Covered	T3,T4,T7
1	1	1	Covered	T2,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T8
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T3,T5,T7
1	1	1	Covered	T3,T4,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T7
0	1	Covered	T3,T5,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T8,T9
1	1	0	Covered	T7,T8,T9
1	1	1	Covered	T7,T8,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T8,T9
1	1	0	Covered	T7,T8,T9
1	1	1	Covered	T7,T8,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T7,T8
1	1	0	Covered	T4,T7,T8
1	1	1	Covered	T4,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T8
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T8
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T7,T8
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T5,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T7,T8
1	1	0	Covered	T7,T8,T9
1	1	1	Covered	T3,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T9,T10
1	1	0	Covered	T7,T8,T9
1	1	1	Covered	T7,T8,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T3,T4

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T4
1	1	Covered	T7,T8,T9

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T4
1	1	Covered	T7,T8,T9

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T7,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T3,T4
1	1	Covered	T5,T7,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T7,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T4
1	1	Covered	T7,T8,T9

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T4,T8,T9

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T39,T40
1	0	Covered	T8,T9,T10

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T49,T39
1	0	Covered	T4,T9,T10
1	1	Covered	T8,T39,T40

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T49

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T49,T36

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T12,T49

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T12,T49

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T12,T40

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T12,T40

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	34013055	33700396	0	0
gen_filter_match[0].MatchCheck00_A	34013055	9266842	0	0
gen_filter_match[0].MatchCheck01_A	34013055	2738442	0	0
gen_filter_match[0].MatchCheck10_A	34013055	2646801	0	0
gen_filter_match[0].MatchCheck11_A	34013055	19048311	0	0
gen_filter_match[1].MatchCheck00_A	34013055	11959848	0	0
gen_filter_match[1].MatchCheck01_A	34013055	1206017	0	0
gen_filter_match[1].MatchCheck10_A	34013055	1205410	0	0
gen_filter_match[1].MatchCheck11_A	34013055	19329121	0	0
gen_filter_match[2].MatchCheck00_A	34013055	12010828	0	0
gen_filter_match[2].MatchCheck01_A	34013055	671999	0	0
gen_filter_match[2].MatchCheck10_A	34013055	733855	0	0
gen_filter_match[2].MatchCheck11_A	34013055	20283714	0	0
gen_filter_match[3].MatchCheck00_A	34013055	13217705	0	0
gen_filter_match[3].MatchCheck01_A	34013055	227477	0	0
gen_filter_match[3].MatchCheck10_A	34013055	237541	0	0
gen_filter_match[3].MatchCheck11_A	34013055	20017673	0	0
gen_filter_match[4].MatchCheck00_A	34013055	11789536	0	0
gen_filter_match[4].MatchCheck01_A	34013055	32532	0	0
gen_filter_match[4].MatchCheck10_A	34013055	95	0	0
gen_filter_match[4].MatchCheck11_A	34013055	21878233	0	0
gen_filter_match[5].MatchCheck00_A	34013055	12431517	0	0
gen_filter_match[5].MatchCheck01_A	34013055	33426	0	0
gen_filter_match[5].MatchCheck10_A	34013055	33655	0	0
gen_filter_match[5].MatchCheck11_A	34013055	21201798	0	0
gen_filter_match[6].MatchCheck00_A	34013055	12558873	0	0
gen_filter_match[6].MatchCheck01_A	34013055	19	0	0
gen_filter_match[6].MatchCheck10_A	34013055	129	0	0
gen_filter_match[6].MatchCheck11_A	34013055	21141375	0	0
gen_filter_match[7].MatchCheck00_A	34013055	13375377	0	0
gen_filter_match[7].MatchCheck01_A	34013055	261487	0	0
gen_filter_match[7].MatchCheck10_A	34013055	175973	0	0
gen_filter_match[7].MatchCheck11_A	34013055	19887559	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	33700396	0	0
T1	8878	8788	0	0
T2	26045	23305	0	0
T3	33700	33623	0	0
T4	51432	51342	0	0
T5	40309	39926	0	0
T6	1124	1070	0	0
T7	96979	96902	0	0
T8	40389	40306	0	0
T9	82075	81990	0	0
T13	77	18	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	9266842	0	0
T1	8878	8788	0	0
T2	26045	22737	0	0
T3	33700	4	0	0
T4	51432	3	0	0
T5	40309	39926	0	0
T6	1124	1070	0	0
T7	96979	4	0	0
T8	40389	4	0	0
T9	82075	3	0	0
T13	77	18	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	2738442	0	0
T3	33700	33619	0	0
T4	51432	0	0	0
T5	40309	0	0	0
T6	1124	0	0	0
T7	96979	0	0	0
T8	40389	0	0	0
T9	82075	0	0	0
T10	39993	0	0	0
T11	23759	0	0	0
T12	0	33066	0	0
T13	77	0	0	0
T36	0	35091	0	0
T47	0	3525	0	0
T49	0	32119	0	0
T58	0	34156	0	0
T76	0	33365	0	0
T106	0	37107	0	0
T163	0	33419	0	0
T164	0	33408	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	2646801	0	0
T9	82075	1	0	0
T10	39993	0	0	0
T11	23759	0	0	0
T12	65766	0	0	0
T33	7259	0	0	0
T38	0	1	0	0
T48	23903	0	0	0
T49	96490	0	0	0
T50	66409	0	0	0
T51	0	8	0	0
T55	0	1	0	0
T57	0	32792	0	0
T59	65155	0	0	0
T66	0	32466	0	0
T164	0	32917	0	0
T165	0	32996	0	0
T166	0	33221	0	0
T167	0	35683	0	0
T168	5688	0	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	19048311	0	0
T2	26045	568	0	0
T3	33700	0	0	0
T4	51432	51339	0	0
T5	40309	0	0	0
T6	1124	0	0	0
T7	96979	96898	0	0
T8	40389	40302	0	0
T9	82075	81986	0	0
T10	39993	39898	0	0
T11	0	205	0	0
T13	77	0	0	0
T48	0	1247	0	0
T49	0	31610	0	0
T50	0	66323	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	11959848	0	0
T1	8878	8788	0	0
T2	26045	23305	0	0
T3	33700	4	0	0
T4	51432	3	0	0
T5	40309	7445	0	0
T6	1124	1070	0	0
T7	96979	4	0	0
T8	40389	4	0	0
T9	82075	3	0	0
T13	77	18	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	1206017	0	0
T33	7259	0	0	0
T36	35185	0	0	0
T37	1162	0	0	0
T38	97487	0	0	0
T39	35530	0	0	0
T40	111069	0	0	0
T49	96490	31610	0	0
T50	66409	0	0	0
T59	65155	0	0	0
T168	5688	0	0	0
T169	0	35237	0	0
T170	0	31905	0	0
T171	0	32071	0	0
T172	0	62806	0	0
T173	0	34163	0	0
T174	0	35723	0	0
T175	0	38300	0	0
T176	0	34417	0	0
T177	0	2	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	1205410	0	0
T4	51432	51339	0	0
T5	40309	0	0	0
T6	1124	0	0	0
T7	96979	0	0	0
T8	40389	0	0	0
T9	82075	2	0	0
T10	39993	1	0	0
T11	23759	0	0	0
T13	77	0	0	0
T38	0	1	0	0
T43	0	33281	0	0
T46	0	35624	0	0
T48	23903	0	0	0
T51	0	7	0	0
T55	0	2	0	0
T92	0	33130	0	0
T178	0	32281	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	19329121	0	0
T3	33700	33619	0	0
T4	51432	0	0	0
T5	40309	32481	0	0
T6	1124	0	0	0
T7	96979	96898	0	0
T8	40389	40302	0	0
T9	82075	81985	0	0
T10	39993	39897	0	0
T11	23759	0	0	0
T12	0	65673	0	0
T13	77	0	0	0
T49	0	32694	0	0
T50	0	66323	0	0
T59	0	65059	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	12010828	0	0
T1	8878	8788	0	0
T2	26045	23305	0	0
T3	33700	33623	0	0
T4	51432	51342	0	0
T5	40309	39926	0	0
T6	1124	1070	0	0
T7	96979	4	0	0
T8	40389	4	0	0
T9	82075	3	0	0
T13	77	18	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	671999	0	0
T39	35530	35458	0	0
T40	111069	0	0	0
T41	107	0	0	0
T42	1128	0	0	0
T43	66031	0	0	0
T44	637	0	0	0
T58	0	32635	0	0
T63	0	33251	0	0
T65	121915	0	0	0
T66	32521	0	0	0
T68	14207	0	0	0
T108	0	52359	0	0
T109	0	34851	0	0
T163	0	33377	0	0
T164	0	32353	0	0
T165	98170	0	0	0
T179	0	1	0	0
T180	0	33736	0	0
T181	0	33454	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	733855	0	0
T9	82075	2	0	0
T10	39993	1	0	0
T11	23759	0	0	0
T12	65766	0	0	0
T29	0	1	0	0
T33	7259	0	0	0
T38	0	2	0	0
T48	23903	0	0	0
T49	96490	0	0	0
T50	66409	0	0	0
T51	0	53143	0	0
T59	65155	0	0	0
T168	5688	0	0	0
T182	0	1	0	0
T183	0	2	0	0
T184	0	1	0	0
T185	0	3	0	0
T186	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	20283714	0	0
T7	96979	96898	0	0
T8	40389	40302	0	0
T9	82075	81985	0	0
T10	39993	39897	0	0
T11	23759	0	0	0
T12	65766	65673	0	0
T36	0	35091	0	0
T38	0	97402	0	0
T40	0	34760	0	0
T48	23903	0	0	0
T49	96490	0	0	0
T50	66409	66323	0	0
T59	0	65059	0	0
T168	5688	0	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	13217705	0	0
T1	8878	8788	0	0
T2	26045	23305	0	0
T3	33700	33623	0	0
T4	51432	51342	0	0
T5	40309	39926	0	0
T6	1124	1070	0	0
T7	96979	4	0	0
T8	40389	4	0	0
T9	82075	3	0	0
T13	77	18	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	227477	0	0
T24	0	33092	0	0
T40	111069	36558	0	0
T41	107	0	0	0
T42	1128	0	0	0
T43	66031	0	0	0
T44	637	0	0	0
T65	121915	0	0	0
T66	32521	0	0	0
T68	14207	0	0	0
T94	64	0	0	0
T163	0	1	0	0
T165	98170	0	0	0
T177	0	1	0	0
T187	0	36919	0	0
T188	0	1	0	0
T189	0	32565	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	0	2	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	237541	0	0
T9	82075	2	0	0
T10	39993	1	0	0
T11	23759	0	0	0
T12	65766	0	0	0
T29	0	1	0	0
T33	7259	0	0	0
T38	0	1	0	0
T48	23903	0	0	0
T49	96490	0	0	0
T50	66409	0	0	0
T51	0	10	0	0
T57	0	4	0	0
T59	65155	0	0	0
T168	5688	0	0	0
T182	0	1	0	0
T183	0	4	0	0
T185	0	2	0	0
T193	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	20017673	0	0
T7	96979	96898	0	0
T8	40389	40302	0	0
T9	82075	81985	0	0
T10	39993	39897	0	0
T11	23759	0	0	0
T12	65766	65673	0	0
T36	0	35091	0	0
T38	0	97402	0	0
T48	23903	0	0	0
T49	96490	32119	0	0
T50	66409	66323	0	0
T59	0	65059	0	0
T168	5688	0	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	11789536	0	0
T1	8878	8788	0	0
T2	26045	23305	0	0
T3	33700	33623	0	0
T4	51432	3	0	0
T5	40309	39926	0	0
T6	1124	1070	0	0
T7	96979	4	0	0
T8	40389	4	0	0
T9	82075	4	0	0
T13	77	18	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	32532	0	0
T172	95717	0	0	0
T184	73311	0	0	0
T185	100389	0	0	0
T186	99482	0	0	0
T188	103737	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0
T198	0	32522	0	0
T199	0	1	0	0
T200	0	1	0	0
T201	62	0	0	0
T202	58	0	0	0
T203	114311	0	0	0
T204	65871	0	0	0
T205	35894	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	95	0	0
T9	82075	1	0	0
T10	39993	1	0	0
T11	23759	0	0	0
T12	65766	1	0	0
T33	7259	0	0	0
T38	0	1	0	0
T48	23903	0	0	0
T49	96490	0	0	0
T50	66409	0	0	0
T51	0	9	0	0
T55	0	2	0	0
T57	0	3	0	0
T59	65155	0	0	0
T168	5688	0	0	0
T182	0	1	0	0
T193	0	1	0	0
T206	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	21878233	0	0
T4	51432	51339	0	0
T5	40309	0	0	0
T6	1124	0	0	0
T7	96979	96898	0	0
T8	40389	40302	0	0
T9	82075	81985	0	0
T10	39993	39897	0	0
T11	23759	0	0	0
T12	0	32606	0	0
T13	77	0	0	0
T36	0	35091	0	0
T38	0	97402	0	0
T48	23903	0	0	0
T50	0	66323	0	0
T59	0	65059	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	12431517	0	0
T1	8878	8788	0	0
T2	26045	23305	0	0
T3	33700	33623	0	0
T4	51432	51342	0	0
T5	40309	7445	0	0
T6	1124	1070	0	0
T7	96979	4	0	0
T8	40389	4	0	0
T9	82075	4	0	0
T13	77	18	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	33426	0	0
T46	45160	0	0	0
T57	97665	3	0	0
T58	66866	0	0	0
T63	33306	0	0	0
T85	1659	0	0	0
T124	0	33404	0	0
T163	66853	1	0	0
T179	0	1	0	0
T188	0	1	0	0
T194	0	1	0	0
T204	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0
T209	0	3	0	0
T210	32644	0	0	0
T211	97626	0	0	0
T212	42324	0	0	0
T213	28386	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	33655	0	0
T9	82075	1	0	0
T10	39993	1	0	0
T11	23759	0	0	0
T12	65766	1	0	0
T33	7259	0	0	0
T38	0	1	0	0
T48	23903	0	0	0
T49	96490	0	0	0
T50	66409	0	0	0
T51	0	11	0	0
T55	0	2	0	0
T57	0	4	0	0
T59	65155	0	0	0
T163	0	1	0	0
T168	5688	0	0	0
T182	0	1	0	0
T193	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	21201798	0	0
T5	40309	32481	0	0
T6	1124	0	0	0
T7	96979	96898	0	0
T8	40389	40302	0	0
T9	82075	81985	0	0
T10	39993	39897	0	0
T11	23759	0	0	0
T12	65766	32606	0	0
T38	0	97402	0	0
T48	23903	0	0	0
T49	96490	31610	0	0
T50	0	66323	0	0
T59	0	65059	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	12558873	0	0
T1	8878	8788	0	0
T2	26045	23305	0	0
T3	33700	4	0	0
T4	51432	51342	0	0
T5	40309	39926	0	0
T6	1124	1070	0	0
T7	96979	4	0	0
T8	40389	4	0	0
T9	82075	4	0	0
T13	77	18	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	19	0	0
T172	95717	0	0	0
T177	0	2	0	0
T179	105276	1	0	0
T184	73311	1	0	0
T185	100389	0	0	0
T186	99482	0	0	0
T188	103737	0	0	0
T195	0	1	0	0
T201	62	0	0	0
T202	58	0	0	0
T203	114311	0	0	0
T204	65871	1	0	0
T207	0	1	0	0
T209	0	2	0	0
T214	0	1	0	0
T215	0	1	0	0
T216	0	1	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	129	0	0
T9	82075	1	0	0
T10	39993	1	0	0
T11	23759	0	0	0
T12	65766	1	0	0
T33	7259	0	0	0
T38	0	1	0	0
T46	0	2	0	0
T48	23903	0	0	0
T49	96490	0	0	0
T50	66409	0	0	0
T51	0	8	0	0
T59	65155	0	0	0
T163	0	1	0	0
T168	5688	0	0	0
T182	0	1	0	0
T193	0	1	0	0
T206	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	21141375	0	0
T3	33700	33619	0	0
T4	51432	0	0	0
T5	40309	0	0	0
T6	1124	0	0	0
T7	96979	96898	0	0
T8	40389	40302	0	0
T9	82075	81985	0	0
T10	39993	39897	0	0
T11	23759	0	0	0
T12	0	32606	0	0
T13	77	0	0	0
T36	0	35091	0	0
T49	0	31610	0	0
T50	0	66323	0	0
T59	0	65059	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	13375377	0	0
T1	8878	8788	0	0
T2	26045	23305	0	0
T3	33700	33623	0	0
T4	51432	51342	0	0
T5	40309	39926	0	0
T6	1124	1070	0	0
T7	96979	4	0	0
T8	40389	4	0	0
T9	82075	4	0	0
T13	77	18	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	261487	0	0
T43	66031	32668	0	0
T44	637	0	0	0
T57	0	3	0	0
T65	121915	0	0	0
T66	32521	0	0	0
T68	14207	0	0	0
T92	98930	0	0	0
T94	64	0	0	0
T165	98170	0	0	0
T188	0	1	0	0
T217	0	31740	0	0
T218	0	33048	0	0
T219	0	1	0	0
T220	0	32135	0	0
T221	0	1	0	0
T222	0	32872	0	0
T223	0	31906	0	0
T224	39711	0	0	0
T225	98863	0	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	175973	0	0
T9	82075	1	0	0
T10	39993	1	0	0
T11	23759	0	0	0
T12	65766	1	0	0
T29	0	1	0	0
T33	7259	0	0	0
T38	0	2	0	0
T46	0	3	0	0
T48	23903	0	0	0
T49	96490	0	0	0
T50	66409	0	0	0
T51	0	4	0	0
T57	0	3	0	0
T59	65155	0	0	0
T168	5688	0	0	0
T182	0	1	0	0
T193	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34013055	19887559	0	0
T7	96979	96898	0	0
T8	40389	40302	0	0
T9	82075	81985	0	0
T10	39993	39897	0	0
T11	23759	0	0	0
T12	65766	32606	0	0
T36	0	35091	0	0
T38	0	97401	0	0
T48	23903	0	0	0
T49	96490	31610	0	0
T50	66409	66323	0	0
T59	0	65059	0	0
T168	5688	0	0	0