Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1142	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1198	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1160	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1204	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1024	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1261	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1272	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1180	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1178	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1230	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1159	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1150	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1085	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1233	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1199	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1189	0	0
adc_en_ctl_rd_A	2147483647	968	0	0
adc_fsm_rst_rd_A	2147483647	851	0	0
adc_intr_ctl_rd_A	2147483647	1229	0	0
adc_lp_sample_ctl_rd_A	2147483647	885	0	0
adc_pd_ctl_rd_A	2147483647	1136	0	0
adc_sample_ctl_rd_A	2147483647	940	0	0
adc_wakeup_ctl_rd_A	2147483647	944	0	0
intr_enable_rd_A	2147483647	1719	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1142	0	0
T14	635898	28	0	0
T15	0	13	0	0
T16	0	16	0	0
T17	0	37	0	0
T18	0	32	0	0
T19	0	45	0	0
T20	0	32	0	0
T21	0	29	0	0
T22	0	8	0	0
T23	0	34	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1198	0	0
T14	635898	24	0	0
T15	0	24	0	0
T16	0	19	0	0
T17	0	46	0	0
T18	0	16	0	0
T19	0	40	0	0
T20	0	36	0	0
T21	0	22	0	0
T22	0	7	0	0
T23	0	25	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1160	0	0
T14	635898	20	0	0
T15	0	6	0	0
T16	0	17	0	0
T17	0	43	0	0
T18	0	13	0	0
T19	0	55	0	0
T20	0	43	0	0
T21	0	38	0	0
T22	0	4	0	0
T23	0	22	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1204	0	0
T14	635898	20	0	0
T15	0	15	0	0
T16	0	29	0	0
T17	0	30	0	0
T18	0	17	0	0
T19	0	31	0	0
T20	0	42	0	0
T21	0	36	0	0
T22	0	13	0	0
T23	0	24	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1024	0	0
T14	635898	16	0	0
T15	0	9	0	0
T16	0	16	0	0
T17	0	23	0	0
T18	0	22	0	0
T19	0	41	0	0
T20	0	39	0	0
T21	0	42	0	0
T22	0	5	0	0
T23	0	15	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1261	0	0
T14	635898	12	0	0
T15	0	23	0	0
T16	0	35	0	0
T17	0	39	0	0
T18	0	19	0	0
T19	0	44	0	0
T20	0	35	0	0
T21	0	54	0	0
T22	0	18	0	0
T23	0	16	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1272	0	0
T14	635898	16	0	0
T15	0	19	0	0
T16	0	10	0	0
T17	0	32	0	0
T18	0	23	0	0
T19	0	50	0	0
T20	0	36	0	0
T21	0	34	0	0
T22	0	23	0	0
T23	0	9	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1180	0	0
T14	635898	28	0	0
T15	0	4	0	0
T16	0	6	0	0
T17	0	27	0	0
T18	0	15	0	0
T19	0	35	0	0
T20	0	52	0	0
T21	0	32	0	0
T22	0	16	0	0
T23	0	20	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1178	0	0
T14	635898	10	0	0
T15	0	15	0	0
T16	0	22	0	0
T17	0	31	0	0
T18	0	16	0	0
T19	0	32	0	0
T20	0	51	0	0
T21	0	41	0	0
T22	0	20	0	0
T23	0	16	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1230	0	0
T14	635898	24	0	0
T15	0	32	0	0
T16	0	12	0	0
T17	0	32	0	0
T18	0	21	0	0
T19	0	34	0	0
T20	0	35	0	0
T21	0	35	0	0
T22	0	12	0	0
T23	0	28	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1159	0	0
T14	635898	11	0	0
T15	0	28	0	0
T16	0	27	0	0
T17	0	26	0	0
T18	0	18	0	0
T19	0	37	0	0
T20	0	51	0	0
T21	0	26	0	0
T22	0	16	0	0
T23	0	20	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1150	0	0
T14	635898	27	0	0
T15	0	24	0	0
T16	0	8	0	0
T17	0	21	0	0
T18	0	9	0	0
T19	0	27	0	0
T20	0	27	0	0
T21	0	38	0	0
T22	0	5	0	0
T23	0	18	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1085	0	0
T14	635898	22	0	0
T15	0	29	0	0
T16	0	19	0	0
T17	0	22	0	0
T18	0	29	0	0
T19	0	30	0	0
T20	0	32	0	0
T21	0	36	0	0
T22	0	1	0	0
T23	0	22	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1233	0	0
T14	635898	22	0	0
T15	0	28	0	0
T16	0	21	0	0
T17	0	32	0	0
T18	0	15	0	0
T19	0	44	0	0
T20	0	39	0	0
T21	0	36	0	0
T22	0	7	0	0
T23	0	18	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1199	0	0
T14	635898	18	0	0
T15	0	14	0	0
T16	0	8	0	0
T17	0	48	0	0
T18	0	20	0	0
T19	0	21	0	0
T20	0	64	0	0
T21	0	41	0	0
T22	0	16	0	0
T23	0	24	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1189	0	0
T14	635898	12	0	0
T15	0	29	0	0
T16	0	25	0	0
T17	0	62	0	0
T18	0	25	0	0
T19	0	34	0	0
T20	0	53	0	0
T21	0	29	0	0
T22	0	24	0	0
T23	0	10	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	968	0	0
T14	635898	12	0	0
T15	0	22	0	0
T16	0	22	0	0
T17	0	21	0	0
T18	0	25	0	0
T19	0	36	0	0
T20	0	38	0	0
T21	0	38	0	0
T22	0	14	0	0
T23	0	11	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	851	0	0
T14	635898	19	0	0
T15	0	19	0	0
T16	0	26	0	0
T17	0	32	0	0
T18	0	23	0	0
T19	0	30	0	0
T20	0	37	0	0
T21	0	38	0	0
T22	0	17	0	0
T23	0	20	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1229	0	0
T14	635898	13	0	0
T15	0	11	0	0
T16	0	11	0	0
T17	0	39	0	0
T18	0	9	0	0
T19	0	33	0	0
T20	0	31	0	0
T21	0	35	0	0
T22	0	8	0	0
T23	0	9	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	885	0	0
T14	635898	18	0	0
T15	0	29	0	0
T16	0	7	0	0
T17	0	39	0	0
T18	0	23	0	0
T19	0	52	0	0
T20	0	42	0	0
T21	0	39	0	0
T22	0	11	0	0
T23	0	19	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1136	0	0
T14	635898	12	0	0
T15	0	20	0	0
T16	0	11	0	0
T17	0	44	0	0
T18	0	27	0	0
T19	0	27	0	0
T20	0	37	0	0
T21	0	37	0	0
T22	0	6	0	0
T23	0	26	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	940	0	0
T14	635898	25	0	0
T15	0	21	0	0
T16	0	11	0	0
T17	0	51	0	0
T18	0	22	0	0
T19	0	48	0	0
T20	0	25	0	0
T21	0	48	0	0
T22	0	19	0	0
T23	0	11	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	944	0	0
T14	635898	15	0	0
T15	0	18	0	0
T16	0	21	0	0
T17	0	45	0	0
T18	0	20	0	0
T19	0	32	0	0
T20	0	50	0	0
T21	0	22	0	0
T22	0	13	0	0
T23	0	12	0	0
T24	796183	0	0	0
T25	572413	0	0	0
T26	619025	0	0	0
T27	463564	0	0	0
T28	399612	0	0	0
T29	199191	0	0	0
T30	588090	0	0	0
T31	236835	0	0	0
T32	624829	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1719	0	0
T14	0	35	0	0
T15	0	26	0	0
T16	0	33	0	0
T17	0	56	0	0
T18	0	50	0	0
T19	0	35	0	0
T20	0	67	0	0
T33	348509	23	0	0
T34	0	41	0	0
T35	0	23	0	0
T36	172413	0	0	0
T37	581737	0	0	0
T38	487444	0	0	0
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