Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1244128	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1219466

1

T1

1493

T2

351

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2152784	1			T1	2039		T2	446		T15	1
values[0x0]	154986	1			T1	568		T2	95		T3	14
values[0x1]	155824	1			T1	559		T2	92		T3	17

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	996945	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1466649

1

T1

1799

T2

402

T3

18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9338	1			T1	2		T2	2		T5	44
valid_sources[0x01]	13568	1			T1	5		T2	2		T5	63
valid_sources[0x02]	7202	1			T1	5		T2	1		T3	1
valid_sources[0x03]	9950	1			T1	4		T2	1		T5	59
valid_sources[0x04]	9731	1			T1	1		T2	7		T5	53
valid_sources[0x05]	7325	1			T1	5		T2	1		T5	48
valid_sources[0x06]	11938	1			T1	11		T2	4		T5	51
valid_sources[0x07]	7994	1			T1	21		T5	65		T7	4
valid_sources[0x08]	7648	1			T1	9		T2	1		T3	2
valid_sources[0x09]	8147	1			T1	13		T2	3		T5	61
valid_sources[0x0a]	8425	1			T1	1		T5	46		T7	4
valid_sources[0x0b]	7665	1			T1	3		T2	5		T5	53
valid_sources[0x0c]	12245	1			T1	10		T2	2		T5	41
valid_sources[0x0d]	7273	1			T1	12		T2	2		T5	57
valid_sources[0x0e]	8202	1			T1	22		T2	4		T5	50
valid_sources[0x0f]	14598	1			T1	12		T2	1		T5	50
valid_sources[0x10]	9003	1			T1	17		T2	3		T5	61
valid_sources[0x11]	11056	1			T1	19		T2	4		T5	40
valid_sources[0x12]	7906	1			T1	4		T2	2		T5	45
valid_sources[0x13]	7966	1			T1	2		T2	2		T3	1
valid_sources[0x14]	7547	1			T1	6		T2	1		T5	57
valid_sources[0x15]	9491	1			T1	3		T2	3		T5	55
valid_sources[0x16]	7191	1			T1	4		T2	7		T5	61
valid_sources[0x17]	11608	1			T1	4		T2	1		T5	49
valid_sources[0x18]	12766	1			T1	6		T2	2		T5	62
valid_sources[0x19]	12265	1			T1	26		T2	1		T5	46
valid_sources[0x1a]	11954	1			T1	17		T2	1		T5	45
valid_sources[0x1b]	7471	1			T1	2		T2	1		T5	42
valid_sources[0x1c]	7538	1			T1	10		T2	4		T5	46
valid_sources[0x1d]	7781	1			T1	27		T2	4		T3	1
valid_sources[0x1e]	7241	1			T1	16		T2	2		T5	56
valid_sources[0x1f]	11523	1			T1	5		T2	3		T3	1
valid_sources[0x20]	12167	1			T1	1		T2	2		T5	52
valid_sources[0x21]	7209	1			T1	4		T2	6		T5	53
valid_sources[0x22]	7073	1			T1	2		T15	1		T5	50
valid_sources[0x23]	12254	1			T2	5		T5	43		T6	2
valid_sources[0x24]	14332	1			T1	8		T2	5		T5	56
valid_sources[0x25]	7861	1			T1	7		T2	4		T5	53
valid_sources[0x26]	11867	1			T1	3		T2	3		T5	42
valid_sources[0x27]	8780	1			T1	2		T2	3		T5	54
valid_sources[0x28]	7798	1			T1	13		T2	1		T5	55
valid_sources[0x29]	11798	1			T1	3		T2	1		T5	55
valid_sources[0x2a]	7407	1			T1	2		T2	2		T5	49
valid_sources[0x2b]	11873	1			T1	13		T5	43		T7	1
valid_sources[0x2c]	8501	1			T1	2		T2	2		T5	51
valid_sources[0x2d]	8211	1			T1	7		T2	1		T5	41
valid_sources[0x2e]	7325	1			T1	16		T2	5		T5	33
valid_sources[0x2f]	27365	1			T1	15		T2	3		T5	63
valid_sources[0x30]	7951	1			T1	3		T2	2		T5	79
valid_sources[0x31]	7368	1			T1	13		T2	3		T5	56
valid_sources[0x32]	7715	1			T1	15		T2	7		T5	50
valid_sources[0x33]	8405	1			T1	6		T2	2		T5	59
valid_sources[0x34]	7824	1			T1	4		T2	2		T5	45
valid_sources[0x35]	7772	1			T1	9		T2	1		T5	44
valid_sources[0x36]	8832	1			T1	9		T2	3		T5	43
valid_sources[0x37]	11729	1			T1	10		T2	1		T5	55
valid_sources[0x38]	21335	1			T1	15		T2	3		T3	1
valid_sources[0x39]	7750	1			T1	4		T2	5		T5	38
valid_sources[0x3a]	13770	1			T1	5		T2	4		T5	29
valid_sources[0x3b]	12627	1			T1	11		T2	1		T5	49
valid_sources[0x3c]	11596	1			T1	2		T3	1		T5	60
valid_sources[0x3d]	11543	1			T1	12		T2	4		T5	59
valid_sources[0x3e]	8259	1			T1	11		T2	2		T5	56
valid_sources[0x3f]	12343	1			T1	8		T2	5		T5	55
valid_sources[0x40]	7808	1			T1	8		T2	6		T5	41
valid_sources[0x41]	7663	1			T1	32		T2	3		T5	42
valid_sources[0x42]	8855	1			T1	6		T2	2		T5	54
valid_sources[0x43]	7925	1			T1	1		T2	3		T5	48
valid_sources[0x44]	9388	1			T1	2		T2	3		T5	36
valid_sources[0x45]	11933	1			T1	13		T2	4		T5	47
valid_sources[0x46]	7271	1			T1	2		T2	4		T5	50
valid_sources[0x47]	7715	1			T1	13		T2	4		T5	47
valid_sources[0x48]	8146	1			T1	9		T2	5		T3	1
valid_sources[0x49]	9386	1			T1	9		T2	1		T5	53
valid_sources[0x4a]	12429	1			T1	11		T5	37		T6	1
valid_sources[0x4b]	8638	1			T1	4		T2	1		T5	57
valid_sources[0x4c]	9510	1			T1	14		T2	4		T5	54
valid_sources[0x4d]	7500	1			T1	5		T2	1		T5	70
valid_sources[0x4e]	10324	1			T1	6		T2	1		T5	31
valid_sources[0x4f]	7277	1			T1	7		T5	46		T7	3
valid_sources[0x50]	7652	1			T1	6		T5	48		T7	3
valid_sources[0x51]	8382	1			T1	16		T2	1		T5	64
valid_sources[0x52]	16401	1			T1	15		T2	4		T3	1
valid_sources[0x53]	8964	1			T1	921		T2	1		T5	61
valid_sources[0x54]	11787	1			T1	8		T2	4		T5	44
valid_sources[0x55]	8855	1			T1	1		T2	1		T5	55
valid_sources[0x56]	10646	1			T1	5		T5	50		T7	2
valid_sources[0x57]	21159	1			T2	3		T5	55		T6	1
valid_sources[0x58]	7617	1			T1	23		T2	1		T5	33
valid_sources[0x59]	8279	1			T1	4		T2	1		T5	48
valid_sources[0x5a]	11008	1			T1	1		T2	4		T5	46
valid_sources[0x5b]	10752	1			T1	14		T2	2		T5	54
valid_sources[0x5c]	7537	1			T1	6		T2	2		T3	1
valid_sources[0x5d]	7871	1			T1	4		T2	1		T5	56
valid_sources[0x5e]	8567	1			T1	10		T2	2		T5	61
valid_sources[0x5f]	13314	1			T1	4		T2	1		T5	67
valid_sources[0x60]	12039	1			T1	6		T2	5		T5	55
valid_sources[0x61]	7752	1			T1	25		T2	4		T5	57
valid_sources[0x62]	7435	1			T1	6		T2	3		T5	48
valid_sources[0x63]	8528	1			T1	10		T2	1		T15	1
valid_sources[0x64]	7863	1			T1	14		T2	1		T3	1
valid_sources[0x65]	10192	1			T1	7		T2	2		T5	45
valid_sources[0x66]	7193	1			T1	11		T2	6		T5	47
valid_sources[0x67]	7578	1			T1	11		T2	2		T3	1
valid_sources[0x68]	7961	1			T1	6		T2	2		T3	1
valid_sources[0x69]	7445	1			T1	9		T2	6		T5	47
valid_sources[0x6a]	7637	1			T1	11		T2	3		T5	54
valid_sources[0x6b]	19122	1			T1	26		T2	1		T5	49
valid_sources[0x6c]	7672	1			T1	8		T2	5		T5	48
valid_sources[0x6d]	8413	1			T1	9		T2	3		T5	55
valid_sources[0x6e]	7795	1			T1	15		T2	4		T5	53
valid_sources[0x6f]	7546	1			T1	11		T2	3		T5	62
valid_sources[0x70]	8815	1			T1	8		T2	1		T5	65
valid_sources[0x71]	8674	1			T1	7		T2	4		T5	73
valid_sources[0x72]	8299	1			T1	2		T2	2		T5	51
valid_sources[0x73]	7644	1			T1	22		T2	7		T5	47
valid_sources[0x74]	7436	1			T2	3		T3	1		T5	39
valid_sources[0x75]	7445	1			T1	10		T2	2		T5	45
valid_sources[0x76]	10942	1			T1	15		T2	4		T5	50
valid_sources[0x77]	11663	1			T1	6		T2	4		T5	43
valid_sources[0x78]	8209	1			T1	2		T2	5		T5	60
valid_sources[0x79]	12816	1			T1	25		T2	2		T5	47
valid_sources[0x7a]	10021	1			T1	21		T2	1		T5	55
valid_sources[0x7b]	8692	1			T1	9		T2	4		T5	46
valid_sources[0x7c]	8460	1			T1	19		T2	2		T5	61
valid_sources[0x7d]	8502	1			T1	4		T2	3		T5	48
valid_sources[0x7e]	7466	1			T1	16		T2	1		T5	66
valid_sources[0x7f]	9255	1			T1	3		T2	6		T5	55
valid_sources[0x80]	9561	1			T1	7		T2	1		T5	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1072997

1

T1

1051

T2

224

T15

1

values[0x0]

all_enables

biggest_size

84921

1

T1

259

T2

62

T3

7

values[0x1]

all_enables

biggest_size

61548

1

T1

183

T2

65

T3

9