Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30968	1			T1	217		T5	22		T7	9
auto[PWRUP]	124	1			T1	3		T41	1		T44	3
auto[ONEST_0]	88	1			T41	1		T44	5		T55	2
auto[ONEST_021]	15	1			T193	1		T194	1		T195	1
auto[ONEST_1]	81	1			T1	1		T41	2		T44	1
auto[ONEST_DONE]	2	1			T196	1		T197	1		-	-
auto[LP_0]	143	1			T1	2		T41	2		T44	4
auto[LP_021]	20	1			T1	2		T41	1		T198	1
auto[LP_1]	157	1			T1	4		T41	4		T44	2
auto[LP_EVAL]	75	1			T1	2		T44	2		T31	1
auto[LP_SLP]	517	1			T1	3		T9	4		T41	7
auto[LP_PWRUP]	35	1			T1	1		T44	2		T55	1
auto[NP_0]	165	1			T1	1		T41	2		T44	5
auto[NP_021]	38	1			T1	1		T44	1		T31	1
auto[NP_1]	170	1			T1	1		T9	2		T41	1
auto[NP_EVAL]	36	1			T9	1		T44	2		T49	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T36

1

T199

1

T200

1

min

30368

1

T1

215

T5

22

T7

9

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30377	1			T1	215		T5	22		T7	9
pow[0x1]	8	1			T201	1		T202	1		T203	1
pow[0x2]	18	1			T1	2		T9	1		T204	1
pow[0x3]	39	1			T1	1		T44	1		T29	1
pow[0x4]	65	1			T9	1		T41	1		T44	1
pow[0x5]	121	1			T1	2		T9	1		T41	1
pow[0x6]	283	1			T1	3		T9	4		T41	4
pow[0x7]	571	1			T1	5		T9	3		T41	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

192

1

T1

2

T9

1

T44

2

min

29899

1

T1

210

T5

22

T7

9

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29899	1			T1	210		T5	22		T7	9
pow[0x3]	1	1			T205	1		-	-		-	-
pow[0x4]	2	1			T1	1		T206	1		-	-
pow[0x5]	1	1			T193	1		-	-		-	-
pow[0x7]	2	1			T25	1		T207	1		-	-
pow[0x8]	4	1			T1	1		T198	1		T49	1
pow[0x9]	11	1			T208	1		T209	1		T25	1
pow[0xa]	12	1			T44	1		T49	2		T210	2
pow[0xb]	39	1			T1	1		T44	1		T211	2
pow[0xc]	73	1			T44	3		T29	3		T211	2
pow[0xd]	138	1			T44	1		T29	1		T198	1
pow[0xe]	314	1			T1	4		T9	2		T41	6
pow[0xf]	659	1			T1	10		T9	6		T41	14