Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2368	1			T1	17		T2	6		T15	20
auto[PWRUP]	145	1			T1	1		T9	2		T44	2
auto[ONEST_0]	98	1			T1	1		T41	1		T44	1
auto[ONEST_021]	26	1			T9	1		T44	1		T55	1
auto[ONEST_1]	74	1			T41	1		T55	2		T29	3
auto[ONEST_DONE]	3	1			T344	1		T345	1		T346	1
auto[LP_0]	133	1			T1	2		T44	3		T55	1
auto[LP_021]	25	1			T44	1		T198	1		T49	1
auto[LP_1]	149	1			T1	1		T9	1		T41	1
auto[LP_EVAL]	59	1			T16	1		T198	2		T49	3
auto[LP_SLP]	537	1			T1	6		T9	5		T41	6
auto[LP_PWRUP]	18	1			T55	1		T347	2		T19	1
auto[NP_0]	248	1			T1	2		T2	3		T9	1
auto[NP_021]	51	1			T1	2		T29	1		T49	2
auto[NP_1]	240	1			T1	2		T2	1		T44	1
auto[NP_EVAL]	34	1			T1	1		T17	1		T18	1
auto[NP_DONE]	1	1			T267	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T198

1

T196

1

T203

1

min

1956

1

T1

9

T2

10

T15

20

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1966	1			T1	9		T2	10		T15	20
pow[0x1]	8	1			T49	1		T205	1		T348	1
pow[0x2]	32	1			T44	1		T29	1		T49	1
pow[0x3]	33	1			T49	1		T193	2		T50	1
pow[0x4]	76	1			T9	1		T44	3		T55	1
pow[0x5]	143	1			T1	4		T41	1		T44	2
pow[0x6]	277	1			T9	1		T44	6		T55	2
pow[0x7]	559	1			T1	5		T9	9		T41	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

207

1

T1

2

T9

3

T41

2

min

1357

1

T1

8

T2

7

T15

20

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x6]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1359	1			T1	8		T2	7		T15	20
pow[0x1]	13	1			T2	1		T18	2		T23	2
pow[0x2]	32	1			T49	1		T50	1		T18	1
pow[0x3]	42	1			T2	2		T47	1		T49	3
pow[0x4]	73	1			T44	1		T16	2		T49	1
pow[0x8]	10	1			T1	1		T29	1		T347	1
pow[0x9]	11	1			T201	1		T344	1		T310	1
pow[0xa]	17	1			T9	1		T211	1		T198	2
pow[0xb]	36	1			T44	3		T49	2		T193	1
pow[0xc]	72	1			T41	2		T44	1		T55	1
pow[0xd]	144	1			T1	1		T9	1		T41	1
pow[0xe]	299	1			T1	3		T9	4		T41	2
pow[0xf]	619	1			T1	6		T9	2		T41	5