Module Definition
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Module : adc_ctrl_intr
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.00 100.00 96.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_adc_ctrl_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
i_adc_ctrl_intr_o 100.00 100.00 100.00 100.00 100.00
u_match_sync 93.75 100.00 75.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : adc_ctrl_intr
Line No.TotalCoveredPercent
TOTAL2626100.00
CONT_ASSIGN3911100.00
ALWAYS5166100.00
CONT_ASSIGN6411100.00
ALWAYS6866100.00
ALWAYS9566100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN11911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
MISSING_ELSE
64 1 1
68 1 1
69 1 1
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
95 1 1
96 1 1
97 1 1
99 1 1
100 1 1
101 1 1
MISSING_ELSE
106 1 1
111 1 1
112 1 1
113 1 1
115 1 1
119 1 1


Cond Coverage for Module : adc_ctrl_intr
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION ((aon_req_hold_q == '0) && ((|aon_staging_reqs_q)))
             -----------1----------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T9,T61
10CoveredT1,T2,T3
11CoveredT1,T2,T5

 LINE       64
 SUB-EXPRESSION (aon_req_hold_q == '0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       106
 EXPRESSION (cfg_intr_trans_en_i && dst_ack_q && req_hold_q[8])
             ---------1---------    ----2----    ------3------
-1--2--3-StatusTests
011CoveredT2,T11,T13
101CoveredT1,T5,T8
110CoveredT1,T5,T8
111CoveredT1,T5,T8

 LINE       115
 EXPRESSION (cfg_oneshot_done_i && cfg_oneshot_done_en_i)
             ---------1--------    ----------2----------
-1--2-StatusTests
01CoveredT5,T6,T9
10CoveredT1,T2,T9
11CoveredT6,T103,T16

Branch Coverage for Module : adc_ctrl_intr
Line No.TotalCoveredPercent
Branches 11 11 100.00
IF 51 4 4 100.00
IF 68 4 4 100.00
IF 95 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 51 if ((!rst_aon_ni)) -2-: 53 if (aon_ld_req) -3-: 55 if ((|aon_reqs))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T5
0 0 1 Covered T1,T2,T5
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_aon_ni)) -2-: 70 if (aon_ld_req) -3-: 72 if (aon_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T5
0 0 1 Covered T1,T2,T5
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni)) -2-: 100 if (dst_ack)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T5
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%