Module Definition
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Module : prim_subreg
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.62 100.00 92.86 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_intr_state 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_ext_0 94.44 83.33 100.00 100.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_intr_ext_0 94.44 83.33 100.00 100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_ext_1 94.44 83.33 100.00 100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_intr_ext_1 94.44 83.33 100.00 100.00
tb.dut.u_reg.u_intr_enable 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_en_ctl_adc_enable 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_en_ctl_oneshot_mode 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_lp_mode 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_pwrup_time 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_wakeup_time 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_lp_sample_ctl 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_sample_ctl 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_fsm_rst 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_min_v_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cond_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_max_v_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_min_v_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cond_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_max_v_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_min_v_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cond_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_max_v_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_min_v_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cond_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_max_v_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_min_v_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cond_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_max_v_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_min_v_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cond_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_max_v_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_min_v_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cond_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_max_v_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_min_v_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cond_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_max_v_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_min_v_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cond_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_max_v_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_en_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_min_v_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cond_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_max_v_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_en_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_min_v_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cond_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_max_v_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_en_2 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_min_v_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cond_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_max_v_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_en_3 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_min_v_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cond_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_max_v_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_en_4 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_min_v_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cond_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_max_v_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_en_5 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_min_v_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cond_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_max_v_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_en_6 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_min_v_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cond_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_max_v_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_en_7 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_intr_0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_intr_1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_match_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_trans_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_filter_status_match 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_filter_status_trans 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_intr_ctl_match_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_intr_ctl_trans_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_intr_ctl_oneshot_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_intr_status_match 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_intr_status_trans 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_intr_status_oneshot 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Module : prim_subreg ( parameter DW=4,SwAccess=0,RESVAL=7,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_pwrup_time

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=8,SwAccess=0,RESVAL,Mubi=0 + DW=8,SwAccess=3,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_lp_sample_ctl

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_match_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_intr_ctl_match_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_filter_status_match

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_intr_status_match

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T15

Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
65.24 50.00
tb.dut.u_reg.u_intr_state

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_en_ctl_adc_enable

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_en_ctl_oneshot_mode

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_lp_mode

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_fsm_rst

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cond_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cond_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cond_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cond_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cond_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cond_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cond_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cond_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cond_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_en_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cond_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_en_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cond_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_en_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cond_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_en_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cond_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_en_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cond_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_en_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cond_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_en_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cond_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_en_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_trans_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_intr_ctl_trans_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_intr_ctl_oneshot_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_filter_status_trans

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_intr_status_trans

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_intr_status_oneshot

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=16,SwAccess=0,RESVAL=155,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_sample_ctl

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T15

Cond Coverage for Module : prim_subreg ( parameter DW=24,SwAccess=0,RESVAL=1600,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_wakeup_time

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=10,SwAccess=0,RESVAL=0,Mubi=0 + DW=10,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_min_v_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_max_v_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_min_v_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_max_v_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_min_v_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_max_v_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_min_v_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_max_v_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_min_v_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_max_v_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_min_v_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_max_v_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_min_v_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_max_v_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_min_v_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_max_v_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_min_v_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_max_v_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_min_v_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_max_v_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_min_v_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_max_v_2

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_min_v_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_max_v_3

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_min_v_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_max_v_4

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_min_v_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_max_v_5

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_min_v_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_max_v_6

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_min_v_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_max_v_7

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_intr_0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_intr_1

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=2,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
94.44 100.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_ext_0

SCORECOND
94.44 100.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_intr_ext_0

SCORECOND
94.44 100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_ext_1

SCORECOND
94.44 100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_intr_ext_1

TotalCoveredPercent
Conditions2150.00
Logical2150.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%