Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_adc_chn1_filter_ctl_7_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.73	90.00	66.67			78.26	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.67	94.90	67.39			88.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.29	94.12	85.71			83.33	50.00	u_adc_chn_val_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.73	90.00	66.67			78.26	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.67	94.90	67.39			88.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.29	94.12	85.71			83.33	50.00	u_adc_chn_val_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_adc_wakeup_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.72	100.00	95.24			95.65	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.79	100.00	93.48			97.67	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_filter_status_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.58	95.65	78.95			85.71	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.03	97.87	78.57			92.68	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_adc_fsm_state_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
283	1	1
284	1	1
299		unreachable

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		50	45	90.00
CONT_ASSIGN	100	1	1	100.00
ALWAYS	111	3	3	100.00
ALWAYS	121	6	4	66.67
CONT_ASSIGN	135	1	1	100.00
ALWAYS	139	6	6	100.00
ALWAYS	155	10	9	90.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	187	19	17	89.47
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
111	1	1
112	1	1
114	1	1
121	1	1
122	1	1
123	1	1
128	0	1
129	1	1
132	0	1
			MISSING_ELSE
135	1	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
			MISSING_ELSE
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	0	1
161	1	1
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
183	1	1
187	1	1
188	1	1
192	1	1
193	1	1
195	1	1
197	1	1
199	1	1
200	1	1
202	0	1
203	0	1
204	1	1
205	1	1
206	1	1
207	1	1
210	1	1
211	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
			MISSING_ELSE
228	1	1
243	1	1
244	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

	Total	Covered	Percent
Conditions	42	28	66.67
Logical	42	28	66.67
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

	Line No.	Total	Covered	Percent
Branches		23	18	78.26
IF	111	2	2	100.00
IF	121	4	2	50.00
IF	139	4	4	100.00
IF	155	6	5	83.33
CASE	197	7	5	71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	121	if ((!rst_dst_ni))
-2-:	123	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	129	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	139	if ((!rst_dst_ni))
-2-:	141	if (gen_wr_req.dst_lat_d)
-3-:	143	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	if ((!rst_dst_ni))
-2-:	157	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	159	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	161	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	163	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Not Covered
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T8
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	197	case (gen_wr_req.state_q)
-2-:	200	if (gen_wr_req.dst_req)
-3-:	204	if (dst_update)
-4-:	207	if ((dst_qs_o != dst_qs_i))
-5-:	217	if (gen_wr_req.dst_update_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StIdle	1	-	-	-	Not Covered
StIdle	0	1	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	Covered	T1,T2,T8
StIdle	0	0	0	-	Covered	T1,T2,T3
StWait	-	-	-	1	Covered	T1,T2,T3
StWait	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	Not Covered

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wr_req.DstUpdateReqCheck_A	35324983	655544	0	919
gen_wr_req.HwIdSelCheck_A	35324983	655720	0	0

gen_wr_req.DstUpdateReqCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35324983	655544	0	919
T1	57592	811	0	1
T2	9896	219	0	1
T3	4615	30	0	1
T4	7915	51	0	1
T5	110344	2103	0	1
T6	1128	40	0	1
T7	32687	711	0	1
T8	45500	682	0	1
T9	252737	2047	0	1
T10	0	25	0	0
T15	1509	0	0	1

gen_wr_req.HwIdSelCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35324983	655720	0	0
T1	57592	812	0	0
T2	9896	220	0	0
T3	4615	30	0	0
T4	7915	51	0	0
T5	110344	2103	0	0
T6	1128	40	0	0
T7	32687	711	0	0
T8	45500	683	0	0
T9	252737	2048	0	0
T10	0	25	0	0
T15	1509	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		50	45	90.00
CONT_ASSIGN	100	1	1	100.00
ALWAYS	111	3	3	100.00
ALWAYS	121	6	4	66.67
CONT_ASSIGN	135	1	1	100.00
ALWAYS	139	6	6	100.00
ALWAYS	155	10	9	90.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	187	19	17	89.47
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
111	1	1
112	1	1
114	1	1
121	1	1
122	1	1
123	1	1
128	0	1
129	1	1
132	0	1
			MISSING_ELSE
135	1	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
			MISSING_ELSE
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	0	1
161	1	1
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
183	1	1
187	1	1
188	1	1
192	1	1
193	1	1
195	1	1
197	1	1
199	1	1
200	1	1
202	0	1
203	0	1
204	1	1
205	1	1
206	1	1
207	1	1
210	1	1
211	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
			MISSING_ELSE
228	1	1
243	1	1
244	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

	Total	Covered	Percent
Conditions	42	28	66.67
Logical	42	28	66.67
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T5
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

	Line No.	Total	Covered	Percent
Branches		23	18	78.26
IF	111	2	2	100.00
IF	121	4	2	50.00
IF	139	4	4	100.00
IF	155	6	5	83.33
CASE	197	7	5	71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	121	if ((!rst_dst_ni))
-2-:	123	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	129	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	139	if ((!rst_dst_ni))
-2-:	141	if (gen_wr_req.dst_lat_d)
-3-:	143	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	if ((!rst_dst_ni))
-2-:	157	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	159	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	161	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	163	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Not Covered
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T5
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	197	case (gen_wr_req.state_q)
-2-:	200	if (gen_wr_req.dst_req)
-3-:	204	if (dst_update)
-4-:	207	if ((dst_qs_o != dst_qs_i))
-5-:	217	if (gen_wr_req.dst_update_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StIdle	1	-	-	-	Not Covered
StIdle	0	1	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	Covered	T1,T2,T5
StIdle	0	0	0	-	Covered	T1,T2,T3
StWait	-	-	-	1	Covered	T1,T2,T3
StWait	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	Not Covered

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wr_req.DstUpdateReqCheck_A	35324983	639988	0	919
gen_wr_req.HwIdSelCheck_A	35324983	647904	0	0

gen_wr_req.DstUpdateReqCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35324983	639988	0	919
T1	57592	742	0	1
T2	9896	192	0	1
T3	4615	30	0	1
T4	7915	51	0	1
T5	110344	2041	0	1
T6	1128	20	0	1
T7	32687	669	0	1
T8	45500	655	0	1
T9	252737	1996	0	1
T10	0	14	0	0
T15	1509	0	0	1

gen_wr_req.HwIdSelCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35324983	647904	0	0
T1	57592	748	0	0
T2	9896	195	0	0
T3	4615	30	0	0
T4	7915	51	0	0
T5	110344	2053	0	0
T6	1128	20	0	0
T7	32687	679	0	0
T8	45500	665	0	0
T9	252737	2010	0	0
T10	0	14	0	0
T15	1509	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	100	0	0
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100		unreachable
283	1	1
284	1	1
299		unreachable

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		50	50	100.00
CONT_ASSIGN	100	1	1	100.00
ALWAYS	111	3	3	100.00
ALWAYS	121	6	6	100.00
CONT_ASSIGN	135	1	1	100.00
ALWAYS	139	6	6	100.00
ALWAYS	155	10	10	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	187	19	19	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
111	1	1
112	1	1
114	1	1
121	1	1
122	1	1
123	1	1
128	1	1
129	1	1
132	1	1
			MISSING_ELSE
135	1	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
			MISSING_ELSE
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
183	1	1
187	1	1
188	1	1
192	1	1
193	1	1
195	1	1
197	1	1
199	1	1
200	1	1
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
210	1	1
211	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
			MISSING_ELSE
228	1	1
243	1	1
244	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T61
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T56,T57,T58
1	1	Covered	T59,T56,T60

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T59,T56,T60

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T59,T56,T60

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T56,T57,T58
1	1	Covered	T1,T2,T5

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T59,T56,T60
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T9,T61

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T9,T61
0	1	0	Covered	T1,T2,T5
1	0	0	Covered	T1,T2,T5

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
IF	111	2	2	100.00
IF	121	4	4	100.00
IF	139	4	4	100.00
IF	155	6	6	100.00
CASE	197	7	6	85.71

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	121	if ((!rst_dst_ni))
-2-:	123	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	129	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T59,T56,T60
0	0	1	Covered	T59,T56,T60
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	139	if ((!rst_dst_ni))
-2-:	141	if (gen_wr_req.dst_lat_d)
-3-:	143	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T9,T61
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	if ((!rst_dst_ni))
-2-:	157	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	159	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	161	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	163	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T5
0	0	1	-	-	Covered	T1,T2,T5
0	0	0	1	-	Covered	T1,T2,T5
0	0	0	0	1	Covered	T1,T9,T61
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	197	case (gen_wr_req.state_q)
-2-:	200	if (gen_wr_req.dst_req)
-3-:	204	if (dst_update)
-4-:	207	if ((dst_qs_o != dst_qs_i))
-5-:	217	if (gen_wr_req.dst_update_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StIdle	1	-	-	-	Covered	T1,T2,T5
StIdle	0	1	-	-	Covered	T1,T2,T5
StIdle	0	0	1	-	Covered	T1,T9,T61
StIdle	0	0	0	-	Covered	T1,T2,T3
StWait	-	-	-	1	Covered	T1,T2,T5
StWait	-	-	-	0	Covered	T1,T2,T5
default	-	-	-	-	Not Covered

---

Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wr_req.DstUpdateReqCheck_A	35324983	15789	0	919
gen_wr_req.HwIdSelCheck_A	35324983	15852	0	0

gen_wr_req.DstUpdateReqCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35324983	15789	0	919
T1	57592	17	0	1
T2	9896	4	0	1
T3	4615	0	0	1
T4	7915	0	0	1
T5	110344	35	0	1
T6	1128	0	0	1
T7	32687	18	0	1
T8	45500	19	0	1
T9	252737	35	0	1
T11	0	17	0	0
T12	0	28	0	0
T13	0	66	0	0
T14	0	36	0	0
T15	1509	0	0	1

gen_wr_req.HwIdSelCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35324983	15852	0	0
T1	57592	18	0	0
T2	9896	4	0	0
T3	4615	0	0	0
T4	7915	0	0	0
T5	110344	35	0	0
T6	1128	0	0	0
T7	32687	18	0	0
T8	45500	19	0	0
T9	252737	36	0	0
T11	0	17	0	0
T12	0	28	0	0
T13	0	66	0	0
T14	0	36	0	0
T15	1509	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	100	0	0
ALWAYS	111	3	3	100.00
ALWAYS	121	6	4	66.67
CONT_ASSIGN	135	1	1	100.00
ALWAYS	139	6	6	100.00
ALWAYS	155	9	9	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	187	17	17	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100		unreachable
111	1	1
112	1	1
114	1	1
121	1	1
122	1	1
123	1	1
128	0	1
129	1	1
132	0	1
			MISSING_ELSE
135	1	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
			MISSING_ELSE
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162		excluded
			Exclude Annotation: VC_COV_UNR
163	1	1
164	1	1
			MISSING_ELSE
183	1	1
187	1	1
188	1	1
192	1	1
193	1	1
195	1	1
197	1	1
199	1	1
200	1	1
202	1	1
203	1	1
204	1	1
205		unreachable
206		unreachable
207	1	1
210	1	1
211	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
			MISSING_ELSE
228	1	1
243	1	1
244	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

	Total	Covered	Percent
Conditions	38	30	78.95
Logical	38	30	78.95
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T47,T16
1	0	Not Covered
1	1	Not Covered

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T2,T47,T16
1	1	1	Not Covered

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T47,T16
1	0	Not Covered

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Not Covered
1	1	Covered	T2,T47,T16

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Excluded		VC_COV_UNR

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T47,T16

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T2,T47,T16
1	0	0	Covered	T1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T47,T16

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T47,T16
1	1	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

	Line No.	Total	Covered	Percent
Branches		21	18	85.71
IF	111	2	2	100.00
IF	121	4	2	50.00
IF	139	4	4	100.00
IF	155	5	5	100.00
CASE	197	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	121	if ((!rst_dst_ni))
-2-:	123	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	129	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	139	if ((!rst_dst_ni))
-2-:	141	if (gen_wr_req.dst_lat_d)
-3-:	143	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T47,T16
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	if ((!rst_dst_ni))
-2-:	157	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	159	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	161	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	163	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests	Exclude Annotation
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Covered	T2,T47,T16
0	0	0	1	-	Excluded		VC_COV_UNR
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	197	case (gen_wr_req.state_q)
-2-:	200	if (gen_wr_req.dst_req)
-3-:	204	if (dst_update)
-4-:	207	if ((dst_qs_o != dst_qs_i))
-5-:	217	if (gen_wr_req.dst_update_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StIdle	1	-	-	-	Covered	T2,T47,T16
StIdle	0	1	-	-	Unreachable
StIdle	0	0	1	-	Covered	T1,T2,T3
StIdle	0	0	0	-	Covered	T1,T2,T3
StWait	-	-	-	1	Covered	T1,T2,T3
StWait	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	Not Covered

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wr_req.DstUpdateReqCheck_A	35324983	0	0	919
gen_wr_req.HwIdSelCheck_A	35324983	3325227	0	0

gen_wr_req.DstUpdateReqCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35324983	0	0	919

gen_wr_req.HwIdSelCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35324983	3325227	0	0
T1	57592	4295	0	0
T2	9896	961	0	0
T3	4615	179	0	0
T4	7915	308	0	0
T5	110344	11023	0	0
T6	1128	120	0	0
T7	32687	3344	0	0
T8	45500	4073	0	0
T9	252737	10143	0	0
T10	0	82	0	0
T15	1509	0	0	0