Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1194643	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1168036

1

T4

1

T5

5

T1

456

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2063044	1			T4	1		T5	1		T1	857
values[0x0]	149124	1			T5	10		T1	50		T16	9
values[0x1]	150511	1			T4	3		T5	4		T1	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	957054	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1405625

1

T4

2

T5

6

T1

555

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14453	1			T1	2		T2	14		T7	21
valid_sources[0x01]	6890	1			T1	1		T2	42		T7	23
valid_sources[0x02]	20072	1			T1	4		T2	15		T6	3
valid_sources[0x03]	12316	1			T1	2		T2	13		T7	33
valid_sources[0x04]	6749	1			T1	5		T2	25		T6	10
valid_sources[0x05]	7372	1			T1	4		T2	23		T7	40
valid_sources[0x06]	7961	1			T1	7		T2	16		T7	31
valid_sources[0x07]	15293	1			T1	4		T2	26		T6	9
valid_sources[0x08]	7164	1			T1	2		T2	19		T6	4
valid_sources[0x09]	6706	1			T1	1		T2	15		T7	44
valid_sources[0x0a]	6841	1			T1	1		T2	13		T7	49
valid_sources[0x0b]	10146	1			T1	4		T2	25		T7	28
valid_sources[0x0c]	7215	1			T1	1		T2	20		T7	34
valid_sources[0x0d]	7345	1			T1	3		T2	17		T6	3
valid_sources[0x0e]	14953	1			T1	4		T2	15		T6	19
valid_sources[0x0f]	12075	1			T5	1		T1	4		T2	19
valid_sources[0x10]	7554	1			T1	3		T2	27		T6	4
valid_sources[0x11]	7538	1			T1	6		T2	9		T7	27
valid_sources[0x12]	14939	1			T1	4		T2	20		T6	3
valid_sources[0x13]	9772	1			T1	5		T2	10		T7	30
valid_sources[0x14]	6996	1			T1	7		T2	24		T6	6
valid_sources[0x15]	11559	1			T1	5		T2	25		T6	3
valid_sources[0x16]	20005	1			T1	2		T2	11		T6	6
valid_sources[0x17]	7275	1			T1	3		T2	25		T6	13
valid_sources[0x18]	7853	1			T1	1		T2	16		T7	35
valid_sources[0x19]	7094	1			T1	2		T2	14		T6	3
valid_sources[0x1a]	6761	1			T1	2		T2	16		T6	5
valid_sources[0x1b]	8090	1			T1	3		T2	12		T7	48
valid_sources[0x1c]	11151	1			T1	8		T2	28		T6	1
valid_sources[0x1d]	9905	1			T5	4		T1	5		T2	23
valid_sources[0x1e]	11212	1			T1	2		T2	22		T6	16
valid_sources[0x1f]	7064	1			T1	7		T2	21		T6	5
valid_sources[0x20]	7424	1			T1	2		T2	28		T6	7
valid_sources[0x21]	6849	1			T1	3		T2	26		T7	32
valid_sources[0x22]	7054	1			T1	5		T2	24		T6	1
valid_sources[0x23]	7109	1			T1	3		T2	21		T7	33
valid_sources[0x24]	6976	1			T1	3		T2	11		T6	14
valid_sources[0x25]	7824	1			T1	2		T2	13		T7	20
valid_sources[0x26]	8012	1			T1	2		T2	24		T7	42
valid_sources[0x27]	8841	1			T1	2		T2	12		T7	16
valid_sources[0x28]	7837	1			T1	2		T2	20		T6	9
valid_sources[0x29]	11178	1			T1	2		T2	21		T6	2
valid_sources[0x2a]	7219	1			T1	1		T2	20		T7	19
valid_sources[0x2b]	6868	1			T1	2		T2	20		T6	6
valid_sources[0x2c]	9871	1			T1	3		T2	15		T7	28
valid_sources[0x2d]	8542	1			T5	1		T1	6		T2	22
valid_sources[0x2e]	7267	1			T1	4		T2	18		T6	2
valid_sources[0x2f]	12330	1			T1	3		T2	10		T6	9
valid_sources[0x30]	6607	1			T1	7		T2	23		T6	6
valid_sources[0x31]	7893	1			T1	4		T2	19		T7	35
valid_sources[0x32]	11404	1			T1	1		T2	21		T7	25
valid_sources[0x33]	6657	1			T1	6		T2	20		T6	4
valid_sources[0x34]	7998	1			T1	3		T2	16		T7	16
valid_sources[0x35]	10742	1			T1	8		T2	26		T6	1
valid_sources[0x36]	9944	1			T2	12		T3	16		T7	47
valid_sources[0x37]	7146	1			T1	5		T2	21		T6	1
valid_sources[0x38]	15468	1			T1	7		T2	32		T7	33
valid_sources[0x39]	25592	1			T1	3		T2	21		T6	13
valid_sources[0x3a]	7348	1			T1	5		T2	22		T6	6
valid_sources[0x3b]	7247	1			T1	2		T2	19		T7	31
valid_sources[0x3c]	6977	1			T1	2		T2	25		T7	49
valid_sources[0x3d]	7166	1			T1	5		T2	17		T7	30
valid_sources[0x3e]	7944	1			T1	1		T2	13		T6	3
valid_sources[0x3f]	11348	1			T1	5		T2	21		T7	23
valid_sources[0x40]	7010	1			T1	7		T2	22		T6	1
valid_sources[0x41]	11043	1			T1	1		T2	23		T7	25
valid_sources[0x42]	7876	1			T1	2		T2	22		T6	2
valid_sources[0x43]	7249	1			T1	5		T2	19		T7	43
valid_sources[0x44]	6990	1			T1	6		T2	18		T6	16
valid_sources[0x45]	7400	1			T4	4		T1	3		T2	22
valid_sources[0x46]	11459	1			T1	3		T2	17		T6	4
valid_sources[0x47]	7437	1			T1	8		T2	15		T6	2
valid_sources[0x48]	7736	1			T1	4		T2	18		T7	26
valid_sources[0x49]	6833	1			T1	1		T2	17		T6	10
valid_sources[0x4a]	8291	1			T1	6		T2	14		T6	4
valid_sources[0x4b]	8432	1			T1	5		T2	34		T7	31
valid_sources[0x4c]	12052	1			T1	4		T2	23		T3	12
valid_sources[0x4d]	7589	1			T1	4		T2	15		T6	7
valid_sources[0x4e]	9695	1			T1	3		T2	28		T7	24
valid_sources[0x4f]	7013	1			T1	9		T16	15		T2	16
valid_sources[0x50]	7014	1			T1	8		T2	18		T6	1
valid_sources[0x51]	21512	1			T1	4		T2	22		T6	2
valid_sources[0x52]	8106	1			T2	30		T6	13		T7	28
valid_sources[0x53]	6973	1			T1	1		T2	18		T6	9
valid_sources[0x54]	6938	1			T1	6		T2	37		T6	7
valid_sources[0x55]	8150	1			T1	1		T2	21		T7	33
valid_sources[0x56]	7343	1			T5	5		T1	3		T2	23
valid_sources[0x57]	8610	1			T1	6		T2	21		T6	6
valid_sources[0x58]	7845	1			T1	5		T2	24		T6	2
valid_sources[0x59]	11237	1			T1	1		T2	14		T7	28
valid_sources[0x5a]	20189	1			T1	4		T2	20		T6	14
valid_sources[0x5b]	7990	1			T1	4		T2	28		T6	20
valid_sources[0x5c]	9367	1			T1	2		T2	18		T7	30
valid_sources[0x5d]	9999	1			T1	3		T2	22		T6	6
valid_sources[0x5e]	9310	1			T1	6		T2	14		T6	1
valid_sources[0x5f]	9179	1			T1	3		T2	15		T6	5
valid_sources[0x60]	12278	1			T1	4		T2	23		T7	37
valid_sources[0x61]	8034	1			T1	6		T2	29		T7	42
valid_sources[0x62]	11051	1			T1	2		T2	22		T6	3
valid_sources[0x63]	11116	1			T1	4		T2	18		T7	28
valid_sources[0x64]	7444	1			T1	1		T2	14		T6	4
valid_sources[0x65]	16689	1			T1	3		T2	7		T6	6
valid_sources[0x66]	14474	1			T1	2		T2	18		T6	26
valid_sources[0x67]	8451	1			T1	3		T2	23		T7	19
valid_sources[0x68]	13340	1			T1	5		T2	21		T7	27
valid_sources[0x69]	15407	1			T1	6		T2	17		T3	6
valid_sources[0x6a]	7515	1			T5	1		T1	4		T2	20
valid_sources[0x6b]	7150	1			T1	1		T2	17		T6	2
valid_sources[0x6c]	9139	1			T1	7		T2	23		T6	7
valid_sources[0x6d]	17764	1			T1	4		T2	12		T7	36
valid_sources[0x6e]	7033	1			T1	4		T2	15		T7	25
valid_sources[0x6f]	7466	1			T1	2		T2	10		T6	9
valid_sources[0x70]	7316	1			T2	18		T7	45		T8	30
valid_sources[0x71]	8103	1			T1	3		T2	30		T7	30
valid_sources[0x72]	6980	1			T1	6		T2	27		T6	2
valid_sources[0x73]	7560	1			T1	5		T2	25		T7	27
valid_sources[0x74]	12909	1			T1	2		T2	13		T7	42
valid_sources[0x75]	6841	1			T1	2		T2	27		T6	1
valid_sources[0x76]	8085	1			T1	7		T2	23		T7	19
valid_sources[0x77]	7100	1			T1	7		T2	12		T6	3
valid_sources[0x78]	6760	1			T1	5		T2	17		T6	1
valid_sources[0x79]	10222	1			T1	3		T2	18		T6	20
valid_sources[0x7a]	7333	1			T1	3		T2	20		T7	22
valid_sources[0x7b]	6972	1			T1	3		T2	18		T7	49
valid_sources[0x7c]	7985	1			T1	10		T2	20		T7	24
valid_sources[0x7d]	6850	1			T1	2		T2	13		T6	27
valid_sources[0x7e]	11453	1			T1	2		T2	16		T7	27
valid_sources[0x7f]	7853	1			T2	21		T6	3		T7	25
valid_sources[0x80]	7015	1			T1	5		T2	18		T6	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1029284

1

T4

1

T5

1

T1

410

values[0x0]

all_enables

biggest_size

80284

1

T5

3

T1

31

T16

4

values[0x1]

all_enables

biggest_size

58468

1

T5

1

T1

15

T16

2