Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30614	1			T1	7		T2	19		T6	10
auto[PWRUP]	110	1			T9	1		T43	1		T46	1
auto[ONEST_0]	71	1			T45	3		T42	1		T43	2
auto[ONEST_021]	22	1			T49	1		T171	2		T172	1
auto[ONEST_1]	70	1			T9	1		T45	1		T44	1
auto[ONEST_DONE]	5	1			T173	1		T174	1		T175	1
auto[LP_0]	153	1			T9	1		T45	2		T42	2
auto[LP_021]	43	1			T43	1		T44	4		T50	2
auto[LP_1]	152	1			T9	3		T45	1		T42	2
auto[LP_EVAL]	69	1			T9	1		T45	1		T42	1
auto[LP_SLP]	529	1			T9	2		T45	10		T42	9
auto[LP_PWRUP]	37	1			T9	2		T43	1		T35	1
auto[NP_0]	148	1			T9	2		T45	1		T42	1
auto[NP_021]	36	1			T9	1		T44	1		T36	1
auto[NP_1]	178	1			T9	5		T45	3		T42	2
auto[NP_EVAL]	33	1			T46	1		T176	1		T177	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T44

1

T173

1

T172

1

min

30048

1

T1

7

T2

19

T6

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30055	1			T1	7		T2	19		T6	10
pow[0x1]	9	1			T174	2		T178	1		T179	1
pow[0x2]	19	1			T42	1		T35	1		T44	1
pow[0x3]	34	1			T49	1		T44	2		T180	1
pow[0x4]	74	1			T45	2		T42	1		T46	1
pow[0x5]	138	1			T45	2		T42	1		T49	1
pow[0x6]	283	1			T9	1		T45	3		T42	2
pow[0x7]	559	1			T9	8		T45	8		T42	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

215

1

T9

3

T45

2

T42

3

min

29510

1

T1

7

T2

19

T6

10

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29510	1			T1	7		T2	19		T6	10
pow[0x5]	1	1			T181	1		-	-		-	-
pow[0x6]	2	1			T173	1		T182	1		-	-
pow[0x7]	3	1			T172	1		T180	1		T183	1
pow[0x8]	3	1			T45	1		T118	1		T184	1
pow[0x9]	9	1			T38	1		T171	1		T185	1
pow[0xa]	20	1			T177	1		T186	1		T172	1
pow[0xb]	32	1			T43	1		T35	1		T176	1
pow[0xc]	81	1			T9	1		T45	1		T35	1
pow[0xd]	155	1			T9	1		T45	2		T42	1
pow[0xe]	335	1			T9	4		T45	9		T42	3
pow[0xf]	663	1			T9	5		T45	10		T42	8