Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2425	1			T17	20		T9	20		T10	6
auto[PWRUP]	146	1			T9	1		T45	3		T42	3
auto[ONEST_0]	82	1			T9	2		T35	1		T46	1
auto[ONEST_021]	25	1			T37	1		T50	1		T176	1
auto[ONEST_1]	101	1			T9	1		T42	2		T43	1
auto[ONEST_DONE]	5	1			T44	1		T326	1		T26	1
auto[LP_0]	139	1			T9	3		T45	3		T42	2
auto[LP_021]	36	1			T42	2		T43	1		T44	1
auto[LP_1]	127	1			T45	2		T42	2		T43	1
auto[LP_EVAL]	66	1			T42	1		T43	2		T35	1
auto[LP_SLP]	562	1			T9	9		T10	1		T11	1
auto[LP_PWRUP]	22	1			T9	2		T44	2		T37	1
auto[NP_0]	237	1			T9	2		T10	1		T11	2
auto[NP_021]	56	1			T9	1		T45	2		T49	1
auto[NP_1]	238	1			T9	3		T10	2		T45	4
auto[NP_EVAL]	33	1			T11	1		T43	1		T18	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

13

1

T43

1

T37

1

T176

1

min

1948

1

T17

20

T9

12

T10

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1956	1			T17	20		T9	12		T10	10
pow[0x1]	14	1			T49	1		T176	1		T47	1
pow[0x2]	16	1			T49	1		T38	1		T327	1
pow[0x3]	54	1			T9	1		T35	1		T37	1
pow[0x4]	74	1			T9	1		T43	1		T46	1
pow[0x5]	146	1			T9	2		T45	1		T42	3
pow[0x6]	286	1			T9	2		T11	1		T45	4
pow[0x7]	584	1			T9	3		T11	1		T45	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

224

1

T9

4

T45

6

T42

3

min

1344

1

T17

20

T9

3

T10

7

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1350	1			T17	20		T9	3		T10	7
pow[0x1]	10	1			T11	2		T37	1		T186	1
pow[0x2]	28	1			T38	3		T242	1		T321	1
pow[0x3]	55	1			T10	2		T18	2		T36	3
pow[0x4]	41	1			T10	1		T35	4		T18	3
pow[0x6]	1	1			T328	1		-	-		-	-
pow[0x7]	5	1			T327	1		T178	1		T248	1
pow[0x8]	5	1			T44	1		T48	1		T267	1
pow[0x9]	14	1			T35	1		T46	1		T49	1
pow[0xa]	22	1			T43	1		T46	1		T44	1
pow[0xb]	31	1			T46	1		T36	1		T176	1
pow[0xc]	67	1			T42	1		T35	1		T46	1
pow[0xd]	158	1			T9	1		T45	1		T42	2
pow[0xe]	308	1			T9	6		T45	4		T42	2
pow[0xf]	676	1			T9	15		T45	7		T42	8