Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1900	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1904	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2050	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2148	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1750	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1890	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1808	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2000	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2028	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1897	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1839	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1856	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1929	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2077	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1966	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1763	0	0
adc_en_ctl_rd_A	2147483647	1710	0	0
adc_fsm_rst_rd_A	2147483647	1607	0	0
adc_intr_ctl_rd_A	2147483647	2092	0	0
adc_lp_sample_ctl_rd_A	2147483647	1612	0	0
adc_pd_ctl_rd_A	2147483647	1739	0	0
adc_sample_ctl_rd_A	2147483647	1552	0	0
adc_wakeup_ctl_rd_A	2147483647	1543	0	0
intr_enable_rd_A	2147483647	2385	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1900	0	0
T11	382379	23	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	18	0	0
T19	0	18	0	0
T20	0	4	0	0
T21	0	15	0	0
T22	0	13	0	0
T23	0	37	0	0
T24	0	48	0	0
T25	0	15	0	0
T26	0	28	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1904	0	0
T11	382379	12	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	7	0	0
T19	0	8	0	0
T20	0	2	0	0
T21	0	7	0	0
T22	0	10	0	0
T23	0	31	0	0
T24	0	28	0	0
T25	0	29	0	0
T26	0	22	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2050	0	0
T11	382379	26	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	30	0	0
T19	0	19	0	0
T20	0	3	0	0
T21	0	15	0	0
T22	0	7	0	0
T23	0	49	0	0
T24	0	18	0	0
T25	0	27	0	0
T26	0	40	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2148	0	0
T11	382379	13	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	21	0	0
T19	0	20	0	0
T20	0	9	0	0
T21	0	14	0	0
T22	0	16	0	0
T23	0	48	0	0
T24	0	21	0	0
T25	0	25	0	0
T26	0	41	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1750	0	0
T11	382379	21	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	8	0	0
T19	0	22	0	0
T20	0	12	0	0
T21	0	22	0	0
T22	0	15	0	0
T23	0	46	0	0
T24	0	36	0	0
T25	0	23	0	0
T26	0	36	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1890	0	0
T11	382379	7	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	15	0	0
T19	0	19	0	0
T21	0	16	0	0
T22	0	20	0	0
T23	0	42	0	0
T24	0	32	0	0
T25	0	22	0	0
T26	0	40	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0
T32	0	21	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1808	0	0
T11	382379	17	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	22	0	0
T19	0	20	0	0
T20	0	5	0	0
T21	0	6	0	0
T22	0	12	0	0
T23	0	27	0	0
T24	0	38	0	0
T25	0	16	0	0
T26	0	30	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2000	0	0
T11	382379	20	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	27	0	0
T19	0	6	0	0
T20	0	18	0	0
T21	0	34	0	0
T22	0	24	0	0
T23	0	43	0	0
T24	0	29	0	0
T25	0	8	0	0
T26	0	30	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2028	0	0
T11	382379	12	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	19	0	0
T19	0	21	0	0
T20	0	12	0	0
T21	0	17	0	0
T22	0	14	0	0
T23	0	56	0	0
T24	0	28	0	0
T25	0	17	0	0
T26	0	32	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1897	0	0
T11	382379	9	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	21	0	0
T19	0	9	0	0
T20	0	15	0	0
T21	0	21	0	0
T22	0	10	0	0
T23	0	36	0	0
T24	0	47	0	0
T25	0	29	0	0
T26	0	39	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1839	0	0
T11	382379	27	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	20	0	0
T19	0	15	0	0
T20	0	24	0	0
T21	0	17	0	0
T22	0	17	0	0
T23	0	35	0	0
T24	0	23	0	0
T25	0	13	0	0
T26	0	18	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1856	0	0
T11	382379	12	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	21	0	0
T19	0	23	0	0
T20	0	18	0	0
T21	0	26	0	0
T22	0	13	0	0
T23	0	42	0	0
T24	0	52	0	0
T25	0	27	0	0
T26	0	46	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1929	0	0
T11	382379	16	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	22	0	0
T19	0	22	0	0
T20	0	9	0	0
T21	0	22	0	0
T22	0	28	0	0
T23	0	37	0	0
T24	0	24	0	0
T25	0	22	0	0
T26	0	47	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2077	0	0
T11	382379	34	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	21	0	0
T19	0	18	0	0
T20	0	10	0	0
T21	0	28	0	0
T22	0	35	0	0
T23	0	21	0	0
T24	0	36	0	0
T25	0	38	0	0
T26	0	36	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1966	0	0
T11	382379	32	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	17	0	0
T19	0	9	0	0
T20	0	7	0	0
T21	0	10	0	0
T22	0	16	0	0
T23	0	36	0	0
T24	0	33	0	0
T25	0	21	0	0
T26	0	51	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1763	0	0
T11	382379	20	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	18	0	0
T19	0	29	0	0
T20	0	13	0	0
T21	0	13	0	0
T22	0	12	0	0
T23	0	27	0	0
T24	0	40	0	0
T25	0	20	0	0
T26	0	37	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1710	0	0
T11	382379	14	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	26	0	0
T19	0	28	0	0
T21	0	16	0	0
T22	0	24	0	0
T23	0	31	0	0
T24	0	18	0	0
T25	0	25	0	0
T26	0	42	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0
T32	0	21	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1607	0	0
T11	382379	16	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	18	0	0
T19	0	14	0	0
T20	0	14	0	0
T21	0	8	0	0
T22	0	27	0	0
T23	0	26	0	0
T24	0	36	0	0
T25	0	23	0	0
T26	0	52	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2092	0	0
T11	382379	8	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	17	0	0
T19	0	30	0	0
T20	0	25	0	0
T21	0	11	0	0
T22	0	27	0	0
T23	0	51	0	0
T24	0	39	0	0
T25	0	17	0	0
T26	0	44	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1612	0	0
T11	382379	22	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	19	0	0
T19	0	6	0	0
T20	0	10	0	0
T21	0	18	0	0
T22	0	5	0	0
T23	0	43	0	0
T24	0	16	0	0
T25	0	14	0	0
T26	0	41	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1739	0	0
T11	382379	19	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	15	0	0
T19	0	18	0	0
T20	0	4	0	0
T21	0	22	0	0
T22	0	10	0	0
T23	0	48	0	0
T24	0	28	0	0
T25	0	24	0	0
T26	0	47	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1552	0	0
T11	382379	26	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	18	0	0
T19	0	11	0	0
T20	0	22	0	0
T21	0	14	0	0
T22	0	25	0	0
T23	0	42	0	0
T24	0	31	0	0
T25	0	19	0	0
T26	0	23	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1543	0	0
T11	382379	14	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	16	0	0
T19	0	21	0	0
T20	0	4	0	0
T21	0	22	0	0
T22	0	27	0	0
T23	0	29	0	0
T24	0	43	0	0
T25	0	13	0	0
T26	0	19	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2385	0	0
T11	382379	33	0	0
T12	550174	0	0	0
T13	144405	0	0	0
T14	183327	0	0	0
T15	159178	0	0	0
T18	0	22	0	0
T19	0	5	0	0
T20	0	18	0	0
T21	0	22	0	0
T22	0	18	0	0
T23	0	70	0	0
T24	0	49	0	0
T25	0	27	0	0
T27	489739	0	0	0
T28	169801	0	0	0
T29	249023	0	0	0
T30	465946	0	0	0
T31	135203	0	0	0
T33	0	17	0	0