Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1186038	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1158157

1

T1

944

T2

2915

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2051147	1			T1	1715		T2	5097		T4	3966
values[0x0]	146168	1			T1	105		T2	464		T3	18
values[0x1]	146880	1			T1	110		T2	476		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	950187	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1394008

1

T1

1138

T2

3505

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6969	1			T1	7		T2	25		T4	15
valid_sources[0x01]	11184	1			T1	2		T2	14		T4	17
valid_sources[0x02]	6703	1			T1	8		T2	37		T4	24
valid_sources[0x03]	16023	1			T1	22		T2	18		T4	19
valid_sources[0x04]	6960	1			T1	19		T2	35		T4	21
valid_sources[0x05]	8083	1			T2	21		T4	14		T5	8
valid_sources[0x06]	6846	1			T2	12		T4	16		T5	8
valid_sources[0x07]	11199	1			T1	7		T2	30		T4	22
valid_sources[0x08]	6846	1			T1	10		T2	34		T4	14
valid_sources[0x09]	8951	1			T2	31		T4	18		T5	8
valid_sources[0x0a]	8702	1			T2	12		T4	24		T5	11
valid_sources[0x0b]	7140	1			T2	22		T4	23		T5	12
valid_sources[0x0c]	9044	1			T1	17		T2	22		T4	20
valid_sources[0x0d]	7584	1			T1	3		T2	16		T3	1
valid_sources[0x0e]	7685	1			T1	3		T2	41		T4	14
valid_sources[0x0f]	7788	1			T2	25		T4	19		T5	10
valid_sources[0x10]	12013	1			T1	4		T2	34		T4	15
valid_sources[0x11]	6764	1			T1	6		T2	25		T4	18
valid_sources[0x12]	6926	1			T1	4		T2	16		T4	11
valid_sources[0x13]	7064	1			T1	9		T2	25		T4	24
valid_sources[0x14]	7210	1			T1	6		T2	31		T4	7
valid_sources[0x15]	7408	1			T1	15		T2	18		T4	15
valid_sources[0x16]	6807	1			T1	12		T2	21		T4	17
valid_sources[0x17]	7385	1			T1	4		T2	21		T4	17
valid_sources[0x18]	8965	1			T1	7		T2	6		T4	16
valid_sources[0x19]	8769	1			T1	31		T2	14		T4	14
valid_sources[0x1a]	12052	1			T1	4		T2	31		T4	25
valid_sources[0x1b]	7217	1			T1	13		T2	34		T4	13
valid_sources[0x1c]	7558	1			T1	12		T2	35		T4	19
valid_sources[0x1d]	6962	1			T1	8		T2	17		T4	17
valid_sources[0x1e]	6977	1			T1	22		T2	14		T4	6
valid_sources[0x1f]	22752	1			T1	34		T2	14		T4	14
valid_sources[0x20]	9880	1			T1	1		T2	25		T4	14
valid_sources[0x21]	7103	1			T1	5		T2	24		T4	10
valid_sources[0x22]	7745	1			T1	8		T2	25		T4	23
valid_sources[0x23]	15552	1			T1	4		T2	13		T4	16
valid_sources[0x24]	12072	1			T1	16		T2	24		T4	25
valid_sources[0x25]	6984	1			T1	6		T2	10		T4	10
valid_sources[0x26]	6905	1			T1	1		T2	25		T4	14
valid_sources[0x27]	7475	1			T1	10		T2	9		T4	21
valid_sources[0x28]	19535	1			T1	4		T2	24		T4	20
valid_sources[0x29]	13394	1			T1	5		T2	14		T4	15
valid_sources[0x2a]	7415	1			T1	9		T2	28		T4	18
valid_sources[0x2b]	6842	1			T1	7		T2	34		T4	16
valid_sources[0x2c]	7023	1			T1	11		T2	23		T4	27
valid_sources[0x2d]	7287	1			T1	14		T2	18		T4	14
valid_sources[0x2e]	12457	1			T1	16		T2	21		T4	15
valid_sources[0x2f]	6945	1			T1	2		T2	29		T4	14
valid_sources[0x30]	9851	1			T1	21		T2	26		T4	11
valid_sources[0x31]	7325	1			T1	4		T2	23		T4	21
valid_sources[0x32]	10620	1			T1	19		T2	13		T4	15
valid_sources[0x33]	8008	1			T2	9		T4	14		T5	11
valid_sources[0x34]	16489	1			T1	8		T2	21		T4	19
valid_sources[0x35]	10676	1			T1	14		T2	18		T4	15
valid_sources[0x36]	7070	1			T1	13		T2	24		T4	17
valid_sources[0x37]	9054	1			T1	3		T2	23		T4	8
valid_sources[0x38]	8012	1			T1	6		T2	25		T4	13
valid_sources[0x39]	7745	1			T1	6		T2	26		T3	2
valid_sources[0x3a]	8297	1			T1	9		T2	47		T4	15
valid_sources[0x3b]	6922	1			T1	5		T2	9		T4	16
valid_sources[0x3c]	6802	1			T1	5		T2	14		T4	12
valid_sources[0x3d]	6700	1			T1	13		T2	30		T4	14
valid_sources[0x3e]	7077	1			T1	3		T2	22		T4	23
valid_sources[0x3f]	8393	1			T1	6		T2	12		T4	15
valid_sources[0x40]	7107	1			T1	16		T2	20		T4	18
valid_sources[0x41]	8641	1			T1	1		T2	24		T4	13
valid_sources[0x42]	13896	1			T1	4		T2	23		T4	9
valid_sources[0x43]	6840	1			T1	3		T2	23		T4	15
valid_sources[0x44]	7280	1			T1	2		T2	21		T4	11
valid_sources[0x45]	11935	1			T1	11		T2	23		T4	9
valid_sources[0x46]	11484	1			T1	21		T2	26		T4	27
valid_sources[0x47]	6401	1			T1	9		T2	19		T4	23
valid_sources[0x48]	16339	1			T2	24		T4	19		T5	17
valid_sources[0x49]	16699	1			T1	4		T2	9		T4	19
valid_sources[0x4a]	9929	1			T1	5		T2	18		T4	17
valid_sources[0x4b]	9781	1			T1	7		T2	21		T4	17
valid_sources[0x4c]	16649	1			T1	6		T2	34		T4	11
valid_sources[0x4d]	7863	1			T1	8		T2	22		T4	11
valid_sources[0x4e]	14155	1			T1	18		T2	26		T4	15
valid_sources[0x4f]	7020	1			T1	4		T2	21		T4	13
valid_sources[0x50]	7475	1			T1	7		T2	25		T4	12
valid_sources[0x51]	6808	1			T1	1		T2	11		T3	1
valid_sources[0x52]	7280	1			T1	8		T2	12		T4	17
valid_sources[0x53]	7517	1			T1	2		T2	26		T4	15
valid_sources[0x54]	7798	1			T1	2		T2	437		T4	13
valid_sources[0x55]	9643	1			T1	6		T2	20		T4	11
valid_sources[0x56]	12129	1			T1	7		T2	22		T4	16
valid_sources[0x57]	7430	1			T1	18		T2	39		T4	32
valid_sources[0x58]	10733	1			T1	4		T2	29		T4	14
valid_sources[0x59]	6927	1			T1	9		T2	9		T3	4
valid_sources[0x5a]	10072	1			T1	11		T2	18		T4	18
valid_sources[0x5b]	7052	1			T1	4		T2	22		T4	16
valid_sources[0x5c]	9438	1			T1	20		T2	28		T4	18
valid_sources[0x5d]	8619	1			T1	4		T2	24		T3	1
valid_sources[0x5e]	7045	1			T1	10		T2	12		T4	26
valid_sources[0x5f]	7720	1			T1	13		T2	18		T4	24
valid_sources[0x60]	7169	1			T1	5		T2	15		T4	20
valid_sources[0x61]	10610	1			T1	18		T2	18		T4	13
valid_sources[0x62]	6900	1			T1	5		T2	14		T4	13
valid_sources[0x63]	7124	1			T1	3		T2	28		T4	13
valid_sources[0x64]	7373	1			T1	2		T2	20		T4	19
valid_sources[0x65]	9876	1			T1	21		T2	13		T4	11
valid_sources[0x66]	12463	1			T1	12		T2	19		T4	14
valid_sources[0x67]	7005	1			T1	4		T2	7		T4	18
valid_sources[0x68]	7706	1			T2	37		T3	2		T4	20
valid_sources[0x69]	9088	1			T1	11		T2	19		T4	19
valid_sources[0x6a]	8317	1			T1	2		T2	17		T4	10
valid_sources[0x6b]	6908	1			T1	8		T2	17		T4	12
valid_sources[0x6c]	10883	1			T1	6		T2	31		T4	20
valid_sources[0x6d]	11345	1			T1	1		T2	13		T4	16
valid_sources[0x6e]	7515	1			T1	2		T2	29		T4	17
valid_sources[0x6f]	9671	1			T1	8		T2	28		T4	6
valid_sources[0x70]	7019	1			T1	6		T2	22		T4	28
valid_sources[0x71]	7885	1			T1	10		T2	17		T4	11
valid_sources[0x72]	7424	1			T1	5		T2	12		T4	17
valid_sources[0x73]	9686	1			T1	6		T2	14		T4	18
valid_sources[0x74]	8240	1			T1	9		T2	37		T4	14
valid_sources[0x75]	15490	1			T1	9		T2	15		T4	16
valid_sources[0x76]	8517	1			T1	4		T2	27		T4	16
valid_sources[0x77]	7183	1			T1	6		T2	27		T4	13
valid_sources[0x78]	8170	1			T1	6		T2	29		T4	18
valid_sources[0x79]	7876	1			T1	15		T2	15		T4	11
valid_sources[0x7a]	6822	1			T1	10		T2	31		T4	29
valid_sources[0x7b]	7921	1			T1	5		T2	26		T3	3
valid_sources[0x7c]	8562	1			T1	4		T2	12		T4	11
valid_sources[0x7d]	7217	1			T1	7		T2	24		T4	19
valid_sources[0x7e]	8270	1			T1	1		T2	12		T4	13
valid_sources[0x7f]	11549	1			T1	9		T2	43		T4	20
valid_sources[0x80]	7256	1			T1	13		T2	31		T4	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1021754

1

T1

845

T2

2501

T4

1921

values[0x0]

all_enables

biggest_size

79295

1

T1

60

T2

236

T3

9

values[0x1]

all_enables

biggest_size

57108

1

T1

39

T2

178

T3

9