Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30336	1			T1	17		T2	30		T4	9
auto[PWRUP]	113	1			T2	1		T49	1		T51	4
auto[ONEST_0]	78	1			T49	1		T50	2		T51	3
auto[ONEST_021]	18	1			T52	1		T55	1		T17	1
auto[ONEST_1]	83	1			T37	1		T49	1		T50	2
auto[ONEST_DONE]	3	1			T198	1		T199	1		T200	1
auto[LP_0]	130	1			T2	1		T37	1		T49	2
auto[LP_021]	29	1			T51	1		T201	2		T175	1
auto[LP_1]	109	1			T37	1		T51	4		T40	1
auto[LP_EVAL]	56	1			T50	1		T52	2		T55	1
auto[LP_SLP]	497	1			T37	7		T49	4		T50	2
auto[LP_PWRUP]	32	1			T50	1		T55	1		T54	2
auto[NP_0]	151	1			T37	1		T49	2		T50	3
auto[NP_021]	22	1			T40	1		T41	1		T86	1
auto[NP_1]	153	1			T37	1		T50	2		T51	1
auto[NP_EVAL]	33	1			T38	1		T55	2		T43	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T202

1

T203

1

T204

1

min

29752

1

T1

17

T2

28

T4

9

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29766	1			T1	17		T2	28		T4	9
pow[0x1]	6	1			T49	1		T201	1		T205	1
pow[0x2]	16	1			T49	1		T50	1		T51	1
pow[0x3]	38	1			T49	1		T55	1		T43	1
pow[0x4]	57	1			T37	1		T51	1		T38	1
pow[0x5]	116	1			T37	1		T49	1		T50	1
pow[0x6]	268	1			T2	2		T37	2		T49	1
pow[0x7]	539	1			T37	3		T49	3		T50	9

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

212

1

T37

1

T50

2

T51

3

min

29250

1

T1

17

T2

28

T4

9

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29250	1			T1	17		T2	28		T4	9
pow[0x5]	4	1			T206	2		T207	1		T208	1
pow[0x6]	1	1			T209	1		-	-		-	-
pow[0x7]	1	1			T210	1		-	-		-	-
pow[0x8]	7	1			T54	1		T86	1		T211	1
pow[0x9]	10	1			T49	1		T54	1		T212	1
pow[0xa]	16	1			T50	1		T40	1		T213	1
pow[0xb]	38	1			T50	1		T55	1		T43	1
pow[0xc]	67	1			T49	1		T50	1		T51	2
pow[0xd]	128	1			T50	1		T51	1		T52	1
pow[0xe]	303	1			T37	1		T49	2		T50	1
pow[0xf]	605	1			T2	1		T37	7		T49	5