Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2395	1			T2	16		T5	5		T37	27
auto[PWRUP]	133	1			T37	3		T50	3		T39	1
auto[ONEST_0]	81	1			T2	1		T50	4		T51	1
auto[ONEST_021]	24	1			T51	1		T52	1		T86	1
auto[ONEST_1]	78	1			T49	2		T51	1		T38	3
auto[ONEST_DONE]	4	1			T203	1		T205	1		T335	1
auto[LP_0]	131	1			T2	1		T50	2		T40	2
auto[LP_021]	26	1			T50	1		T52	2		T175	1
auto[LP_1]	146	1			T2	1		T49	1		T50	4
auto[LP_EVAL]	73	1			T2	1		T37	1		T49	1
auto[LP_SLP]	533	1			T2	4		T37	3		T49	10
auto[LP_PWRUP]	39	1			T2	1		T37	1		T50	3
auto[NP_0]	228	1			T2	1		T37	1		T49	4
auto[NP_021]	51	1			T40	1		T54	2		T86	1
auto[NP_1]	222	1			T2	1		T37	3		T49	1
auto[NP_EVAL]	27	1			T51	1		T38	3		T13	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T17

1

T203

1

T211

2

min

2021

1

T2

20

T5

5

T37

22

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2035	1			T2	21		T5	5		T37	22
pow[0x1]	9	1			T231	1		T336	1		T337	1
pow[0x2]	30	1			T2	1		T37	1		T44	1
pow[0x3]	37	1			T2	1		T55	1		T43	1
pow[0x4]	68	1			T2	1		T37	1		T50	1
pow[0x5]	125	1			T49	3		T50	2		T40	1
pow[0x6]	287	1			T37	1		T49	4		T50	4
pow[0x7]	549	1			T37	6		T49	5		T50	12

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

214

1

T50

6

T51

1

T38

1

min

1426

1

T2

23

T5

5

T37

16

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1435	1			T2	23		T5	5		T37	16
pow[0x1]	14	1			T39	1		T43	1		T44	1
pow[0x2]	18	1			T38	1		T39	1		T43	1
pow[0x3]	44	1			T37	2		T38	2		T39	1
pow[0x4]	43	1			T38	1		T39	1		T13	4
pow[0x5]	1	1			T338	1		-	-		-	-
pow[0x6]	1	1			T231	1		-	-		-	-
pow[0x7]	2	1			T198	1		T339	1		-	-
pow[0x8]	4	1			T202	1		T209	1		T313	1
pow[0x9]	6	1			T37	1		T231	1		T198	1
pow[0xa]	29	1			T43	1		T86	1		T16	1
pow[0xb]	38	1			T49	1		T55	2		T43	2
pow[0xc]	86	1			T37	2		T50	2		T51	1
pow[0xd]	144	1			T49	3		T50	1		T51	5
pow[0xe]	293	1			T37	4		T49	4		T50	6
pow[0xf]	611	1			T2	2		T37	5		T49	2