Unified Coverage Report :: Module :: adc_ctrl_reg_top

Module : adc_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.85	100.00	99.40			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.96	98.97	96.02	100.00		98.76	96.05

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_chn0_filter_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_0_cond_0	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_0_en_0	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_0_max_v_0	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_0_min_v_0	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_1_cond_1	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_1_en_1	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_1_max_v_1	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_1_min_v_1	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_2_cond_2	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_2_en_2	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_2_max_v_2	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_2_min_v_2	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_3_cond_3	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_3_en_3	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_3_max_v_3	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_3_min_v_3	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_4_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_4_cond_4	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_4_en_4	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_4_max_v_4	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_4_min_v_4	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_5_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_5_cond_5	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_5_en_5	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_5_max_v_5	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_5_min_v_5	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_6_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_6_cond_6	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_6_en_6	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_6_max_v_6	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_6_min_v_6	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_7_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_7_cond_7	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_7_en_7	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_7_max_v_7	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_7_min_v_7	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_0_cond_0	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_0_en_0	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_0_max_v_0	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_0_min_v_0	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_1_cond_1	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_1_en_1	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_1_max_v_1	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_1_min_v_1	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_2_cond_2	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_2_en_2	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_2_max_v_2	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_2_min_v_2	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_3_cond_3	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_3_en_3	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_3_max_v_3	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_3_min_v_3	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_4_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_4_cond_4	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_4_en_4	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_4_max_v_4	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_4_min_v_4	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_5_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_5_cond_5	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_5_en_5	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_5_max_v_5	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_5_min_v_5	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_6_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_6_cond_6	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_6_en_6	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_6_max_v_6	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_6_min_v_6	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_7_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_7_cond_7	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_7_en_7	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_7_max_v_7	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_7_min_v_7	100.00	100.00	100.00			100.00
u_adc_chn_val_0_adc_chn_value_0	100.00	100.00	100.00			100.00
u_adc_chn_val_0_adc_chn_value_ext_0	87.50	62.50	100.00			100.00
u_adc_chn_val_0_adc_chn_value_intr_0	100.00	100.00	100.00			100.00
u_adc_chn_val_0_adc_chn_value_intr_ext_0	87.50	62.50	100.00			100.00
u_adc_chn_val_0_cdc	78.01	95.31	67.24			89.47	60.00
u_adc_chn_val_1_adc_chn_value_1	100.00	100.00	100.00			100.00
u_adc_chn_val_1_adc_chn_value_ext_1	87.50	62.50	100.00			100.00
u_adc_chn_val_1_adc_chn_value_intr_1	100.00	100.00	100.00			100.00
u_adc_chn_val_1_adc_chn_value_intr_ext_1	87.50	62.50	100.00			100.00
u_adc_chn_val_1_cdc	78.01	95.31	67.24			89.47	60.00
u_adc_en_ctl_adc_enable	100.00	100.00	100.00			100.00
u_adc_en_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_en_ctl_oneshot_mode	100.00	100.00	100.00			100.00
u_adc_fsm_rst	100.00	100.00	100.00			100.00
u_adc_fsm_rst_cdc	99.22	100.00	96.88			100.00	100.00
u_adc_fsm_state	100.00	100.00
u_adc_fsm_state_cdc	90.72	98.44	79.69			94.74	90.00
u_adc_intr_ctl_match_en	100.00	100.00	100.00			100.00
u_adc_intr_ctl_oneshot_en	100.00	100.00	100.00			100.00
u_adc_intr_ctl_trans_en	100.00	100.00	100.00			100.00
u_adc_intr_status_match	100.00	100.00	100.00			100.00
u_adc_intr_status_oneshot	100.00	100.00	100.00			100.00
u_adc_intr_status_trans	100.00	100.00	100.00			100.00
u_adc_lp_sample_ctl	100.00	100.00	100.00			100.00
u_adc_lp_sample_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_pd_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_pd_ctl_lp_mode	100.00	100.00	100.00			100.00
u_adc_pd_ctl_pwrup_time	100.00	100.00	100.00			100.00
u_adc_pd_ctl_wakeup_time	100.00	100.00	100.00			100.00
u_adc_sample_ctl	100.00	100.00	100.00			100.00
u_adc_sample_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_wakeup_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_wakeup_ctl_match_en	100.00	100.00	100.00			100.00
u_adc_wakeup_ctl_trans_en	100.00	100.00	100.00			100.00
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_filter_status_cdc	97.74	100.00	92.65			98.31	100.00
u_filter_status_match	100.00	100.00	100.00			100.00
u_filter_status_trans	100.00	100.00	100.00			100.00
u_intr_enable	100.00	100.00	100.00			100.00
u_intr_state	62.59	77.78	50.00			60.00
u_intr_test	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.98	97.14	98.80			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00

Line Coverage for Module : adc_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		340	340	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
ALWAYS	235	3	3	100.00
CONT_ASSIGN	264	1	1	100.00
ALWAYS	276	4	4	100.00
CONT_ASSIGN	306	1	1	100.00
ALWAYS	316	2	2	100.00
CONT_ASSIGN	344	1	1	100.00
ALWAYS	354	2	2	100.00
CONT_ASSIGN	382	1	1	100.00
ALWAYS	392	2	2	100.00
CONT_ASSIGN	420	1	1	100.00
ALWAYS	433	5	5	100.00
CONT_ASSIGN	464	1	1	100.00
ALWAYS	477	5	5	100.00
CONT_ASSIGN	508	1	1	100.00
ALWAYS	521	5	5	100.00
CONT_ASSIGN	552	1	1	100.00
ALWAYS	565	5	5	100.00
CONT_ASSIGN	596	1	1	100.00
ALWAYS	609	5	5	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	653	5	5	100.00
CONT_ASSIGN	684	1	1	100.00
ALWAYS	697	5	5	100.00
CONT_ASSIGN	728	1	1	100.00
ALWAYS	741	5	5	100.00
CONT_ASSIGN	772	1	1	100.00
ALWAYS	785	5	5	100.00
CONT_ASSIGN	816	1	1	100.00
ALWAYS	829	5	5	100.00
CONT_ASSIGN	860	1	1	100.00
ALWAYS	873	5	5	100.00
CONT_ASSIGN	904	1	1	100.00
ALWAYS	917	5	5	100.00
CONT_ASSIGN	948	1	1	100.00
ALWAYS	961	5	5	100.00
CONT_ASSIGN	992	1	1	100.00
ALWAYS	1005	5	5	100.00
CONT_ASSIGN	1036	1	1	100.00
ALWAYS	1049	5	5	100.00
CONT_ASSIGN	1080	1	1	100.00
ALWAYS	1093	5	5	100.00
CONT_ASSIGN	1124	1	1	100.00
ALWAYS	1140	10	10	100.00
ALWAYS	1190	10	10	100.00
ALWAYS	1235	3	3	100.00
CONT_ASSIGN	1264	1	1	100.00
ALWAYS	1279	6	6	100.00
CONT_ASSIGN	1311	1	1	100.00
ALWAYS	1322	4	4	100.00
CONT_ASSIGN	1413	1	1	100.00
CONT_ASSIGN	1427	1	1	100.00
CONT_ASSIGN	1433	1	1	100.00
CONT_ASSIGN	1447	1	1	100.00
CONT_ASSIGN	3452	1	1	100.00
CONT_ASSIGN	3565	1	1	100.00
CONT_ASSIGN	3733	1	1	100.00
CONT_ASSIGN	3957	0	0
ALWAYS	3976	33	33	100.00
CONT_ASSIGN	4011	1	1	100.00
ALWAYS	4015	1	1	100.00
CONT_ASSIGN	4051	1	1	100.00
CONT_ASSIGN	4053	1	1	100.00
CONT_ASSIGN	4054	1	1	100.00
CONT_ASSIGN	4056	1	1	100.00
CONT_ASSIGN	4057	1	1	100.00
CONT_ASSIGN	4059	1	1	100.00
CONT_ASSIGN	4060	1	1	100.00
CONT_ASSIGN	4063	1	1	100.00
CONT_ASSIGN	4067	1	1	100.00
CONT_ASSIGN	4069	1	1	100.00
CONT_ASSIGN	4071	1	1	100.00
CONT_ASSIGN	4073	1	1	100.00
CONT_ASSIGN	4078	1	1	100.00
CONT_ASSIGN	4083	1	1	100.00
CONT_ASSIGN	4088	1	1	100.00
CONT_ASSIGN	4093	1	1	100.00
CONT_ASSIGN	4098	1	1	100.00
CONT_ASSIGN	4103	1	1	100.00
CONT_ASSIGN	4108	1	1	100.00
CONT_ASSIGN	4113	1	1	100.00
CONT_ASSIGN	4118	1	1	100.00
CONT_ASSIGN	4123	1	1	100.00
CONT_ASSIGN	4128	1	1	100.00
CONT_ASSIGN	4133	1	1	100.00
CONT_ASSIGN	4138	1	1	100.00
CONT_ASSIGN	4143	1	1	100.00
CONT_ASSIGN	4148	1	1	100.00
CONT_ASSIGN	4153	1	1	100.00
CONT_ASSIGN	4156	1	1	100.00
CONT_ASSIGN	4159	1	1	100.00
CONT_ASSIGN	4161	1	1	100.00
CONT_ASSIGN	4163	1	1	100.00
CONT_ASSIGN	4165	1	1	100.00
CONT_ASSIGN	4166	1	1	100.00
CONT_ASSIGN	4168	1	1	100.00
CONT_ASSIGN	4170	1	1	100.00
CONT_ASSIGN	4172	1	1	100.00
CONT_ASSIGN	4173	1	1	100.00
ALWAYS	4177	33	33	100.00
ALWAYS	4214	38	38	100.00
CONT_ASSIGN	4334	1	1	100.00
ALWAYS	4336	28	28	100.00
CONT_ASSIGN	4429	1	1	100.00
CONT_ASSIGN	4430	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
79	1	1
91	1	1
92	1	1
120	1	1
121	1	1
235	1	1
236	1	1
237	1	1
264	1	1
276	1	1
277	1	1
278	1	1
279	1	1
306	1	1
316	1	1
317	1	1
344	1	1
354	1	1
355	1	1
382	1	1
392	1	1
393	1	1
420	1	1
433	1	1
434	1	1
435	1	1
436	1	1
437	1	1
464	1	1
477	1	1
478	1	1
479	1	1
480	1	1
481	1	1
508	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
552	1	1
565	1	1
566	1	1
567	1	1
568	1	1
569	1	1
596	1	1
609	1	1
610	1	1
611	1	1
612	1	1
613	1	1
640	1	1
653	1	1
654	1	1
655	1	1
656	1	1
657	1	1
684	1	1
697	1	1
698	1	1
699	1	1
700	1	1
701	1	1
728	1	1
741	1	1
742	1	1
743	1	1
744	1	1
745	1	1
772	1	1
785	1	1
786	1	1
787	1	1
788	1	1
789	1	1
816	1	1
829	1	1
830	1	1
831	1	1
832	1	1
833	1	1
860	1	1
873	1	1
874	1	1
875	1	1
876	1	1
877	1	1
904	1	1
917	1	1
918	1	1
919	1	1
920	1	1
921	1	1
948	1	1
961	1	1
962	1	1
963	1	1
964	1	1
965	1	1
992	1	1
1005	1	1
1006	1	1
1007	1	1
1008	1	1
1009	1	1
1036	1	1
1049	1	1
1050	1	1
1051	1	1
1052	1	1
1053	1	1
1080	1	1
1093	1	1
1094	1	1
1095	1	1
1096	1	1
1097	1	1
1124	1	1
1140	1	1
1141	1	1
1142	1	1
1143	1	1
1144	1	1
1145	1	1
1146	1	1
1147	1	1
1148	1	1
1149	1	1
1190	1	1
1191	1	1
1192	1	1
1193	1	1
1194	1	1
1195	1	1
1196	1	1
1197	1	1
1198	1	1
1199	1	1
1235	1	1
1236	1	1
1237	1	1
1264	1	1
1279	1	1
1280	1	1
1281	1	1
1282	1	1
1283	1	1
1284	1	1
1311	1	1
1322	1	1
1323	1	1
1324	1	1
1325	1	1
1413	1	1
1427	1	1
1433	1	1
1447	1	1
3452	1	1
3565	1	1
3733	1	1
3957		unreachable
3976	1	1
3977	1	1
3978	1	1
3979	1	1
3980	1	1
3981	1	1
3982	1	1
3983	1	1
3984	1	1
3985	1	1
3986	1	1
3987	1	1
3988	1	1
3989	1	1
3990	1	1
3991	1	1
3992	1	1
3993	1	1
3994	1	1
3995	1	1
3996	1	1
3997	1	1
3998	1	1
3999	1	1
4000	1	1
4001	1	1
4002	1	1
4003	1	1
4004	1	1
4005	1	1
4006	1	1
4007	1	1
4008	1	1
4011	1	1
4015	1	1
4051	1	1
4053	1	1
4054	1	1
4056	1	1
4057	1	1
4059	1	1
4060	1	1
4063	1	1
4067	1	1
4069	1	1
4071	1	1
4073	1	1
4078	1	1
4083	1	1
4088	1	1
4093	1	1
4098	1	1
4103	1	1
4108	1	1
4113	1	1
4118	1	1
4123	1	1
4128	1	1
4133	1	1
4138	1	1
4143	1	1
4148	1	1
4153	1	1
4156	1	1
4159	1	1
4161	1	1
4163	1	1
4165	1	1
4166	1	1
4168	1	1
4170	1	1
4172	1	1
4173	1	1
4177	1	1
4178	1	1
4179	1	1
4180	1	1
4181	1	1
4182	1	1
4183	1	1
4184	1	1
4185	1	1
4186	1	1
4187	1	1
4188	1	1
4189	1	1
4190	1	1
4191	1	1
4192	1	1
4193	1	1
4194	1	1
4195	1	1
4196	1	1
4197	1	1
4198	1	1
4199	1	1
4200	1	1
4201	1	1
4202	1	1
4203	1	1
4204	1	1
4205	1	1
4206	1	1
4207	1	1
4208	1	1
4209	1	1
4214	1	1
4215	1	1
4217	1	1
4221	1	1
4225	1	1
4229	1	1
4233	1	1
4236	1	1
4239	1	1
4242	1	1
4245	1	1
4248	1	1
4251	1	1
4254	1	1
4257	1	1
4260	1	1
4263	1	1
4266	1	1
4269	1	1
4272	1	1
4275	1	1
4278	1	1
4281	1	1
4284	1	1
4287	1	1
4290	1	1
4293	1	1
4296	1	1
4299	1	1
4302	1	1
4305	1	1
4308	1	1
4309	1	1
4310	1	1
4314	1	1
4315	1	1
4316	1	1
4320	1	1
4334	1	1
4336	1	1
4337	1	1
4339	1	1
4342	1	1
4345	1	1
4348	1	1
4351	1	1
4354	1	1
4357	1	1
4360	1	1
4363	1	1
4366	1	1
4369	1	1
4372	1	1
4375	1	1
4378	1	1
4381	1	1
4384	1	1
4387	1	1
4390	1	1
4393	1	1
4396	1	1
4399	1	1
4402	1	1
4405	1	1
4408	1	1
4411	1	1
4414	1	1
4429	1	1
4430	1	1

---

Cond Coverage for Module : adc_ctrl_reg_top

	Total	Covered	Percent
Conditions	333	331	99.40
Logical	333	331	99.40
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       72
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T65,T66,T67
1	0	Covered	T60,T61,T62

 LINE       79
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T65,T66,T67
0	1	0	Covered	T60,T61,T62
1	0	0	Covered	T65,T66,T67

 LINE       121
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T60,T61,T62
0	1	0	Covered	T2,T63,T64
1	0	0	Not Covered

 LINE       3977
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_INTR_STATE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3978
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_INTR_ENABLE_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       3979
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_INTR_TEST_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       3980
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ALERT_TEST_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       3981
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_EN_CTL_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3982
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_PD_CTL_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3983
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_LP_SAMPLE_CTL_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3984
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_SAMPLE_CTL_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3985
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_FSM_RST_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3986
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3987
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3988
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_2_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3989
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_3_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3990
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_4_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3991
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_5_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3992
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_6_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3993
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_7_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3994
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3995
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3996
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_2_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3997
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_3_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3998
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_4_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3999
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_5_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       4000
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_6_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       4001
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_7_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       4002
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN_VAL_0_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       4003
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN_VAL_1_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       4004
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_WAKEUP_CTL_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       4005
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_FILTER_STATUS_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       4006
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_INTR_CTL_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       4007
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_INTR_STATUS_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       4008
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_FSM_STATE_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       4011
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       4011
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       4015
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[28] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T63,T64

 LINE       4015
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b0011 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b0011 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
32 (addr_hit[31] & ((|(4'...	Covered	T2,T4,T5
31 (addr_hit[30] & ((|(4'...	Covered	T1,T2,T4
30 (addr_hit[29] & ((|(4'...	Covered	T2,T4,T5
29 (addr_hit[28] & ((|(4'...	Covered	T1,T2,T4
28 (addr_hit[27] & ((|(4'...	Covered	T2,T4,T5
27 (addr_hit[26] & ((|(4'...	Covered	T2,T4,T5
26 (addr_hit[25] & ((|(4'...	Covered	T2,T4,T5
25 (addr_hit[24] & ((|(4'...	Covered	T2,T4,T5
24 (addr_hit[23] & ((|(4'...	Covered	T2,T4,T5
23 (addr_hit[22] & ((|(4'...	Covered	T2,T4,T5
22 (addr_hit[21] & ((|(4'...	Covered	T2,T4,T5
21 (addr_hit[20] & ((|(4'...	Covered	T2,T4,T5
20 (addr_hit[19] & ((|(4'...	Covered	T2,T4,T5
19 (addr_hit[18] & ((|(4'...	Covered	T2,T4,T5
18 (addr_hit[17] & ((|(4'...	Covered	T2,T4,T5
17 (addr_hit[16] & ((|(4'...	Covered	T2,T4,T5
16 (addr_hit[15] & ((|(4'...	Covered	T2,T4,T5
15 (addr_hit[14] & ((|(4'...	Covered	T2,T4,T5
14 (addr_hit[13] & ((|(4'...	Covered	T2,T4,T5
13 (addr_hit[12] & ((|(4'...	Covered	T2,T4,T5
12 (addr_hit[11] & ((|(4'...	Covered	T2,T4,T5
11 (addr_hit[10] & ((|(4'...	Covered	T2,T4,T5
10 (addr_hit[9] & ((|(4'b...	Covered	T2,T4,T5
9 (addr_hit[8] & ((|(4'b...	Covered	T2,T4,T5
8 (addr_hit[7] & ((|(4'b...	Covered	T2,T4,T5
7 (addr_hit[6] & ((|(4'b...	Covered	T2,T4,T5
6 (addr_hit[5] & ((|(4'b...	Covered	T2,T4,T5
5 (addr_hit[4] & ((|(4'b...	Covered	T2,T4,T5
4 (addr_hit[3] & ((|(4'b...	Covered	T2,T4,T5
3 (addr_hit[2] & ((|(4'b...	Covered	T2,T4,T5
2 (addr_hit[1] & ((|(4'b...	Covered	T2,T4,T5
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T4

 LINE       4015
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       4015
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       4015
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       4015
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       4051
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T63,T68,T69
1	1	1	Covered	T2,T4,T5

 LINE       4054
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T68,T69,T70
1	1	1	Covered	T2,T5,T37

 LINE       4057
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T68,T71,T62
1	1	1	Covered	T72,T73,T25

 LINE       4060
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T71,T74,T75
1	1	1	Covered	T1,T2,T3

 LINE       4063
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T3

 LINE       4067
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T4

 LINE       4069
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T70
1	1	1	Covered	T1,T2,T4

 LINE       4071
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T71,T75
1	1	1	Covered	T1,T2,T4

 LINE       4073
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T4

 LINE       4078
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T70,T74
1	1	1	Covered	T1,T2,T4

 LINE       4083
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T70,T75
1	1	1	Covered	T1,T2,T4

 LINE       4088
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T71,T61
1	1	1	Covered	T1,T2,T4

 LINE       4093
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T71,T70
1	1	1	Covered	T1,T2,T4

 LINE       4098
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T69,T71,T76
1	1	1	Covered	T1,T2,T4

 LINE       4103
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T69,T71,T77
1	1	1	Covered	T1,T2,T4

 LINE       4108
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T71,T60
1	1	1	Covered	T1,T2,T4

 LINE       4113
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T4

 LINE       4118
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T4

 LINE       4123
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T4

 LINE       4128
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T2,T68,T69
1	1	1	Covered	T1,T2,T4

 LINE       4133
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T71,T74
1	1	1	Covered	T1,T2,T4

 LINE       4138
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T4

 LINE       4143
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T4

 LINE       4148
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T64,T68,T69
1	1	1	Covered	T1,T2,T4

 LINE       4153
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T68,T71,T70
1	1	1	Covered	T2,T5,T6

 LINE       4156
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T69,T71,T70
1	1	1	Covered	T1,T2,T4

 LINE       4159
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T2,T4,T5

 LINE       4166
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T4

 LINE       4173
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T78,T79,T80
1	1	1	Covered	T2,T37,T38

 LINE       4334
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Branch Coverage for Module : adc_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		65	65	100.00
TERNARY	4011	2	2	100.00
IF	70	3	3	100.00
CASE	4215	33	33	100.00
CASE	4337	27	27	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	4011	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T65,T66,T67
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	4215	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	4337	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : adc_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2147483647	2335241	0	0
reAfterRv	2147483647	2335240	0	0
rePulse	2147483647	2048880	0	0
wePulse	2147483647	286360	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2335241	0	0
T1	736129	1930	0	0
T2	779877	6009	0	0
T3	247977	34	0	0
T4	387994	4228	0	0
T5	382943	12346	0	0
T6	114092	4280	0	0
T7	351983	8372	0	0
T8	442509	52	0	0
T9	384910	931	0	0
T10	246625	2831	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2335240	0	0
T1	736129	1930	0	0
T2	779877	6008	0	0
T3	247977	34	0	0
T4	387994	4228	0	0
T5	382943	12346	0	0
T6	114092	4280	0	0
T7	351983	8372	0	0
T8	442509	52	0	0
T9	384910	931	0	0
T10	246625	2831	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2048880	0	0
T1	736129	1715	0	0
T2	779877	5087	0	0
T3	247977	0	0	0
T4	387994	3966	0	0
T5	382943	11407	0	0
T6	114092	3969	0	0
T7	351983	7872	0	0
T8	442509	0	0	0
T9	384910	822	0	0
T10	246625	2531	0	0
T11	0	12191	0	0
T12	0	848	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	286360	0	0
T1	736129	215	0	0
T2	779877	921	0	0
T3	247977	34	0	0
T4	387994	262	0	0
T5	382943	939	0	0
T6	114092	311	0	0
T7	351983	500	0	0
T8	442509	52	0	0
T9	384910	109	0	0
T10	246625	300	0	0

Line Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
TOTAL		340	340	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
ALWAYS	235	3	3	100.00
CONT_ASSIGN	264	1	1	100.00
ALWAYS	276	4	4	100.00
CONT_ASSIGN	306	1	1	100.00
ALWAYS	316	2	2	100.00
CONT_ASSIGN	344	1	1	100.00
ALWAYS	354	2	2	100.00
CONT_ASSIGN	382	1	1	100.00
ALWAYS	392	2	2	100.00
CONT_ASSIGN	420	1	1	100.00
ALWAYS	433	5	5	100.00
CONT_ASSIGN	464	1	1	100.00
ALWAYS	477	5	5	100.00
CONT_ASSIGN	508	1	1	100.00
ALWAYS	521	5	5	100.00
CONT_ASSIGN	552	1	1	100.00
ALWAYS	565	5	5	100.00
CONT_ASSIGN	596	1	1	100.00
ALWAYS	609	5	5	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	653	5	5	100.00
CONT_ASSIGN	684	1	1	100.00
ALWAYS	697	5	5	100.00
CONT_ASSIGN	728	1	1	100.00
ALWAYS	741	5	5	100.00
CONT_ASSIGN	772	1	1	100.00
ALWAYS	785	5	5	100.00
CONT_ASSIGN	816	1	1	100.00
ALWAYS	829	5	5	100.00
CONT_ASSIGN	860	1	1	100.00
ALWAYS	873	5	5	100.00
CONT_ASSIGN	904	1	1	100.00
ALWAYS	917	5	5	100.00
CONT_ASSIGN	948	1	1	100.00
ALWAYS	961	5	5	100.00
CONT_ASSIGN	992	1	1	100.00
ALWAYS	1005	5	5	100.00
CONT_ASSIGN	1036	1	1	100.00
ALWAYS	1049	5	5	100.00
CONT_ASSIGN	1080	1	1	100.00
ALWAYS	1093	5	5	100.00
CONT_ASSIGN	1124	1	1	100.00
ALWAYS	1140	10	10	100.00
ALWAYS	1190	10	10	100.00
ALWAYS	1235	3	3	100.00
CONT_ASSIGN	1264	1	1	100.00
ALWAYS	1279	6	6	100.00
CONT_ASSIGN	1311	1	1	100.00
ALWAYS	1322	4	4	100.00
CONT_ASSIGN	1413	1	1	100.00
CONT_ASSIGN	1427	1	1	100.00
CONT_ASSIGN	1433	1	1	100.00
CONT_ASSIGN	1447	1	1	100.00
CONT_ASSIGN	3452	1	1	100.00
CONT_ASSIGN	3565	1	1	100.00
CONT_ASSIGN	3733	1	1	100.00
CONT_ASSIGN	3957	0	0
ALWAYS	3976	33	33	100.00
CONT_ASSIGN	4011	1	1	100.00
ALWAYS	4015	1	1	100.00
CONT_ASSIGN	4051	1	1	100.00
CONT_ASSIGN	4053	1	1	100.00
CONT_ASSIGN	4054	1	1	100.00
CONT_ASSIGN	4056	1	1	100.00
CONT_ASSIGN	4057	1	1	100.00
CONT_ASSIGN	4059	1	1	100.00
CONT_ASSIGN	4060	1	1	100.00
CONT_ASSIGN	4063	1	1	100.00
CONT_ASSIGN	4067	1	1	100.00
CONT_ASSIGN	4069	1	1	100.00
CONT_ASSIGN	4071	1	1	100.00
CONT_ASSIGN	4073	1	1	100.00
CONT_ASSIGN	4078	1	1	100.00
CONT_ASSIGN	4083	1	1	100.00
CONT_ASSIGN	4088	1	1	100.00
CONT_ASSIGN	4093	1	1	100.00
CONT_ASSIGN	4098	1	1	100.00
CONT_ASSIGN	4103	1	1	100.00
CONT_ASSIGN	4108	1	1	100.00
CONT_ASSIGN	4113	1	1	100.00
CONT_ASSIGN	4118	1	1	100.00
CONT_ASSIGN	4123	1	1	100.00
CONT_ASSIGN	4128	1	1	100.00
CONT_ASSIGN	4133	1	1	100.00
CONT_ASSIGN	4138	1	1	100.00
CONT_ASSIGN	4143	1	1	100.00
CONT_ASSIGN	4148	1	1	100.00
CONT_ASSIGN	4153	1	1	100.00
CONT_ASSIGN	4156	1	1	100.00
CONT_ASSIGN	4159	1	1	100.00
CONT_ASSIGN	4161	1	1	100.00
CONT_ASSIGN	4163	1	1	100.00
CONT_ASSIGN	4165	1	1	100.00
CONT_ASSIGN	4166	1	1	100.00
CONT_ASSIGN	4168	1	1	100.00
CONT_ASSIGN	4170	1	1	100.00
CONT_ASSIGN	4172	1	1	100.00
CONT_ASSIGN	4173	1	1	100.00
ALWAYS	4177	33	33	100.00
ALWAYS	4214	38	38	100.00
CONT_ASSIGN	4334	1	1	100.00
ALWAYS	4336	28	28	100.00
CONT_ASSIGN	4429	1	1	100.00
CONT_ASSIGN	4430	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
79	1	1
91	1	1
92	1	1
120	1	1
121	1	1
235	1	1
236	1	1
237	1	1
264	1	1
276	1	1
277	1	1
278	1	1
279	1	1
306	1	1
316	1	1
317	1	1
344	1	1
354	1	1
355	1	1
382	1	1
392	1	1
393	1	1
420	1	1
433	1	1
434	1	1
435	1	1
436	1	1
437	1	1
464	1	1
477	1	1
478	1	1
479	1	1
480	1	1
481	1	1
508	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
552	1	1
565	1	1
566	1	1
567	1	1
568	1	1
569	1	1
596	1	1
609	1	1
610	1	1
611	1	1
612	1	1
613	1	1
640	1	1
653	1	1
654	1	1
655	1	1
656	1	1
657	1	1
684	1	1
697	1	1
698	1	1
699	1	1
700	1	1
701	1	1
728	1	1
741	1	1
742	1	1
743	1	1
744	1	1
745	1	1
772	1	1
785	1	1
786	1	1
787	1	1
788	1	1
789	1	1
816	1	1
829	1	1
830	1	1
831	1	1
832	1	1
833	1	1
860	1	1
873	1	1
874	1	1
875	1	1
876	1	1
877	1	1
904	1	1
917	1	1
918	1	1
919	1	1
920	1	1
921	1	1
948	1	1
961	1	1
962	1	1
963	1	1
964	1	1
965	1	1
992	1	1
1005	1	1
1006	1	1
1007	1	1
1008	1	1
1009	1	1
1036	1	1
1049	1	1
1050	1	1
1051	1	1
1052	1	1
1053	1	1
1080	1	1
1093	1	1
1094	1	1
1095	1	1
1096	1	1
1097	1	1
1124	1	1
1140	1	1
1141	1	1
1142	1	1
1143	1	1
1144	1	1
1145	1	1
1146	1	1
1147	1	1
1148	1	1
1149	1	1
1190	1	1
1191	1	1
1192	1	1
1193	1	1
1194	1	1
1195	1	1
1196	1	1
1197	1	1
1198	1	1
1199	1	1
1235	1	1
1236	1	1
1237	1	1
1264	1	1
1279	1	1
1280	1	1
1281	1	1
1282	1	1
1283	1	1
1284	1	1
1311	1	1
1322	1	1
1323	1	1
1324	1	1
1325	1	1
1413	1	1
1427	1	1
1433	1	1
1447	1	1
3452	1	1
3565	1	1
3733	1	1
3957		unreachable
3976	1	1
3977	1	1
3978	1	1
3979	1	1
3980	1	1
3981	1	1
3982	1	1
3983	1	1
3984	1	1
3985	1	1
3986	1	1
3987	1	1
3988	1	1
3989	1	1
3990	1	1
3991	1	1
3992	1	1
3993	1	1
3994	1	1
3995	1	1
3996	1	1
3997	1	1
3998	1	1
3999	1	1
4000	1	1
4001	1	1
4002	1	1
4003	1	1
4004	1	1
4005	1	1
4006	1	1
4007	1	1
4008	1	1
4011	1	1
4015	1	1
4051	1	1
4053	1	1
4054	1	1
4056	1	1
4057	1	1
4059	1	1
4060	1	1
4063	1	1
4067	1	1
4069	1	1
4071	1	1
4073	1	1
4078	1	1
4083	1	1
4088	1	1
4093	1	1
4098	1	1
4103	1	1
4108	1	1
4113	1	1
4118	1	1
4123	1	1
4128	1	1
4133	1	1
4138	1	1
4143	1	1
4148	1	1
4153	1	1
4156	1	1
4159	1	1
4161	1	1
4163	1	1
4165	1	1
4166	1	1
4168	1	1
4170	1	1
4172	1	1
4173	1	1
4177	1	1
4178	1	1
4179	1	1
4180	1	1
4181	1	1
4182	1	1
4183	1	1
4184	1	1
4185	1	1
4186	1	1
4187	1	1
4188	1	1
4189	1	1
4190	1	1
4191	1	1
4192	1	1
4193	1	1
4194	1	1
4195	1	1
4196	1	1
4197	1	1
4198	1	1
4199	1	1
4200	1	1
4201	1	1
4202	1	1
4203	1	1
4204	1	1
4205	1	1
4206	1	1
4207	1	1
4208	1	1
4209	1	1
4214	1	1
4215	1	1
4217	1	1
4221	1	1
4225	1	1
4229	1	1
4233	1	1
4236	1	1
4239	1	1
4242	1	1
4245	1	1
4248	1	1
4251	1	1
4254	1	1
4257	1	1
4260	1	1
4263	1	1
4266	1	1
4269	1	1
4272	1	1
4275	1	1
4278	1	1
4281	1	1
4284	1	1
4287	1	1
4290	1	1
4293	1	1
4296	1	1
4299	1	1
4302	1	1
4305	1	1
4308	1	1
4309	1	1
4310	1	1
4314	1	1
4315	1	1
4316	1	1
4320	1	1
4334	1	1
4336	1	1
4337	1	1
4339	1	1
4342	1	1
4345	1	1
4348	1	1
4351	1	1
4354	1	1
4357	1	1
4360	1	1
4363	1	1
4366	1	1
4369	1	1
4372	1	1
4375	1	1
4378	1	1
4381	1	1
4384	1	1
4387	1	1
4390	1	1
4393	1	1
4396	1	1
4399	1	1
4402	1	1
4405	1	1
4408	1	1
4411	1	1
4414	1	1
4429	1	1
4430	1	1

---

Cond Coverage for Instance : tb.dut.u_reg

	Total	Covered	Percent
Conditions	331	331	100.00
Logical	331	331	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       72
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T65,T66,T67
1	0	Covered	T60,T61,T62

 LINE       79
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T65,T66,T67
0	1	0	Covered	T60,T61,T62
1	0	0	Covered	T65,T66,T67

 LINE       121
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T60,T61,T62
0	1	0	Covered	T2,T63,T64
1	0	0	Excluded		VC_COV_UNR

 LINE       3977
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_INTR_STATE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3978
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_INTR_ENABLE_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       3979
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_INTR_TEST_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       3980
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ALERT_TEST_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       3981
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_EN_CTL_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3982
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_PD_CTL_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3983
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_LP_SAMPLE_CTL_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3984
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_SAMPLE_CTL_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3985
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_FSM_RST_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3986
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3987
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3988
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_2_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3989
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_3_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3990
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_4_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3991
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_5_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3992
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_6_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3993
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN0_FILTER_CTL_7_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3994
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3995
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3996
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_2_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3997
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_3_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3998
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_4_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3999
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_5_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       4000
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_6_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       4001
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN1_FILTER_CTL_7_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       4002
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN_VAL_0_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       4003
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_CHN_VAL_1_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       4004
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_WAKEUP_CTL_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       4005
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_FILTER_STATUS_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       4006
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_INTR_CTL_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       4007
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_INTR_STATUS_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       4008
 EXPRESSION (reg_addr == adc_ctrl_reg_pkg::ADC_CTRL_ADC_FSM_STATE_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       4011
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       4011
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       4015
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[28] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T63,T64

 LINE       4015
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b0011 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b0011 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
32 (addr_hit[31] & ((|(4'...	Covered	T2,T4,T5
31 (addr_hit[30] & ((|(4'...	Covered	T1,T2,T4
30 (addr_hit[29] & ((|(4'...	Covered	T2,T4,T5
29 (addr_hit[28] & ((|(4'...	Covered	T1,T2,T4
28 (addr_hit[27] & ((|(4'...	Covered	T2,T4,T5
27 (addr_hit[26] & ((|(4'...	Covered	T2,T4,T5
26 (addr_hit[25] & ((|(4'...	Covered	T2,T4,T5
25 (addr_hit[24] & ((|(4'...	Covered	T2,T4,T5
24 (addr_hit[23] & ((|(4'...	Covered	T2,T4,T5
23 (addr_hit[22] & ((|(4'...	Covered	T2,T4,T5
22 (addr_hit[21] & ((|(4'...	Covered	T2,T4,T5
21 (addr_hit[20] & ((|(4'...	Covered	T2,T4,T5
20 (addr_hit[19] & ((|(4'...	Covered	T2,T4,T5
19 (addr_hit[18] & ((|(4'...	Covered	T2,T4,T5
18 (addr_hit[17] & ((|(4'...	Covered	T2,T4,T5
17 (addr_hit[16] & ((|(4'...	Covered	T2,T4,T5
16 (addr_hit[15] & ((|(4'...	Covered	T2,T4,T5
15 (addr_hit[14] & ((|(4'...	Covered	T2,T4,T5
14 (addr_hit[13] & ((|(4'...	Covered	T2,T4,T5
13 (addr_hit[12] & ((|(4'...	Covered	T2,T4,T5
12 (addr_hit[11] & ((|(4'...	Covered	T2,T4,T5
11 (addr_hit[10] & ((|(4'...	Covered	T2,T4,T5
10 (addr_hit[9] & ((|(4'b...	Covered	T2,T4,T5
9 (addr_hit[8] & ((|(4'b...	Covered	T2,T4,T5
8 (addr_hit[7] & ((|(4'b...	Covered	T2,T4,T5
7 (addr_hit[6] & ((|(4'b...	Covered	T2,T4,T5
6 (addr_hit[5] & ((|(4'b...	Covered	T2,T4,T5
5 (addr_hit[4] & ((|(4'b...	Covered	T2,T4,T5
4 (addr_hit[3] & ((|(4'b...	Covered	T2,T4,T5
3 (addr_hit[2] & ((|(4'b...	Covered	T2,T4,T5
2 (addr_hit[1] & ((|(4'b...	Covered	T2,T4,T5
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T4

 LINE       4015
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       4015
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       4015
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       4015
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       4015
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       4051
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T63,T68,T69
1	1	1	Covered	T2,T4,T5

 LINE       4054
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T68,T69,T70
1	1	1	Covered	T2,T5,T37

 LINE       4057
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T68,T71,T62
1	1	1	Covered	T72,T73,T25

 LINE       4060
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T71,T74,T75
1	1	1	Covered	T1,T2,T3

 LINE       4063
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T3

 LINE       4067
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T4

 LINE       4069
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T70
1	1	1	Covered	T1,T2,T4

 LINE       4071
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T71,T75
1	1	1	Covered	T1,T2,T4

 LINE       4073
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T4

 LINE       4078
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T70,T74
1	1	1	Covered	T1,T2,T4

 LINE       4083
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T70,T75
1	1	1	Covered	T1,T2,T4

 LINE       4088
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T71,T61
1	1	1	Covered	T1,T2,T4

 LINE       4093
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T71,T70
1	1	1	Covered	T1,T2,T4

 LINE       4098
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T69,T71,T76
1	1	1	Covered	T1,T2,T4

 LINE       4103
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T69,T71,T77
1	1	1	Covered	T1,T2,T4

 LINE       4108
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T71,T60
1	1	1	Covered	T1,T2,T4

 LINE       4113
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T4

 LINE       4118
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T4

 LINE       4123
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T4

 LINE       4128
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T2,T68,T69
1	1	1	Covered	T1,T2,T4

 LINE       4133
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T71,T74
1	1	1	Covered	T1,T2,T4

 LINE       4138
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T4

 LINE       4143
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T4

 LINE       4148
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T64,T68,T69
1	1	1	Covered	T1,T2,T4

 LINE       4153
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T68,T71,T70
1	1	1	Covered	T2,T5,T6

 LINE       4156
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T69,T71,T70
1	1	1	Covered	T1,T2,T4

 LINE       4159
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T2,T4,T5

 LINE       4166
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T69,T71
1	1	1	Covered	T1,T2,T4

 LINE       4173
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T78,T79,T80
1	1	1	Covered	T2,T37,T38

 LINE       4334
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
Branches		65	65	100.00
TERNARY	4011	2	2	100.00
IF	70	3	3	100.00
CASE	4215	33	33	100.00
CASE	4337	27	27	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	4011	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T65,T66,T67
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	4215	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	4337	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2147483647	2335241	0	0
reAfterRv	2147483647	2335240	0	0
rePulse	2147483647	2048880	0	0
wePulse	2147483647	286360	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2335241	0	0
T1	736129	1930	0	0
T2	779877	6009	0	0
T3	247977	34	0	0
T4	387994	4228	0	0
T5	382943	12346	0	0
T6	114092	4280	0	0
T7	351983	8372	0	0
T8	442509	52	0	0
T9	384910	931	0	0
T10	246625	2831	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2335240	0	0
T1	736129	1930	0	0
T2	779877	6008	0	0
T3	247977	34	0	0
T4	387994	4228	0	0
T5	382943	12346	0	0
T6	114092	4280	0	0
T7	351983	8372	0	0
T8	442509	52	0	0
T9	384910	931	0	0
T10	246625	2831	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2048880	0	0
T1	736129	1715	0	0
T2	779877	5087	0	0
T3	247977	0	0	0
T4	387994	3966	0	0
T5	382943	11407	0	0
T6	114092	3969	0	0
T7	351983	7872	0	0
T8	442509	0	0	0
T9	384910	822	0	0
T10	246625	2531	0	0
T11	0	12191	0	0
T12	0	848	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	286360	0	0
T1	736129	215	0	0
T2	779877	921	0	0
T3	247977	34	0	0
T4	387994	262	0	0
T5	382943	939	0	0
T6	114092	311	0	0
T7	351983	500	0	0
T8	442509	52	0	0
T9	384910	109	0	0
T10	246625	300	0	0