Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1205586	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1176197

1

T4

5

T1

1349

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2082274	1			T4	1		T1	2398		T5	1
values[0x0]	149521	1			T4	8		T1	160		T5	1
values[0x1]	149988	1			T4	8		T1	170		T5	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	965828	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1415955

1

T4

5

T1

1648

T5

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7232	1			T1	14		T3	31		T6	4
valid_sources[0x01]	6888	1			T1	5		T2	8		T3	22
valid_sources[0x02]	21308	1			T1	13		T2	46		T3	12
valid_sources[0x03]	11710	1			T1	13		T2	23		T3	26
valid_sources[0x04]	7815	1			T1	10		T2	11		T3	26
valid_sources[0x05]	11195	1			T1	11		T2	3		T3	15
valid_sources[0x06]	12632	1			T1	11		T3	25		T6	11
valid_sources[0x07]	8386	1			T1	8		T2	19		T3	23
valid_sources[0x08]	7004	1			T1	14		T3	19		T6	10
valid_sources[0x09]	11293	1			T1	10		T3	16		T6	11
valid_sources[0x0a]	7104	1			T1	12		T3	46		T6	3
valid_sources[0x0b]	7562	1			T1	12		T2	1		T3	8
valid_sources[0x0c]	11101	1			T1	16		T3	27		T6	10
valid_sources[0x0d]	7666	1			T1	12		T13	1		T3	44
valid_sources[0x0e]	20151	1			T1	11		T2	36		T3	21
valid_sources[0x0f]	7612	1			T1	15		T2	10		T3	46
valid_sources[0x10]	18074	1			T1	12		T3	37		T6	6
valid_sources[0x11]	12673	1			T1	5		T3	19		T6	30
valid_sources[0x12]	6599	1			T1	17		T3	39		T6	4
valid_sources[0x13]	7173	1			T1	15		T2	46		T3	16
valid_sources[0x14]	7031	1			T1	10		T2	7		T3	34
valid_sources[0x15]	16380	1			T1	6		T3	32		T6	8
valid_sources[0x16]	17281	1			T1	7		T2	9		T3	19
valid_sources[0x17]	6826	1			T1	9		T2	7		T3	28
valid_sources[0x18]	6899	1			T1	5		T2	5		T3	53
valid_sources[0x19]	7117	1			T1	12		T2	5		T3	28
valid_sources[0x1a]	7405	1			T1	5		T3	21		T6	9
valid_sources[0x1b]	19924	1			T4	1		T1	15		T2	45
valid_sources[0x1c]	8289	1			T1	5		T3	32		T6	4
valid_sources[0x1d]	11087	1			T1	12		T2	10		T3	24
valid_sources[0x1e]	25210	1			T1	19		T2	5		T3	61
valid_sources[0x1f]	6748	1			T1	7		T2	17		T3	42
valid_sources[0x20]	6721	1			T1	14		T2	19		T3	26
valid_sources[0x21]	10790	1			T4	1		T1	10		T3	29
valid_sources[0x22]	6788	1			T1	10		T2	36		T3	29
valid_sources[0x23]	7477	1			T1	8		T2	1		T3	13
valid_sources[0x24]	7856	1			T1	13		T3	19		T6	9
valid_sources[0x25]	14037	1			T1	6		T2	18		T3	32
valid_sources[0x26]	7381	1			T1	11		T3	27		T6	9
valid_sources[0x27]	8190	1			T1	9		T3	20		T6	9
valid_sources[0x28]	7415	1			T1	14		T2	36		T3	24
valid_sources[0x29]	11039	1			T1	6		T2	25		T3	27
valid_sources[0x2a]	10882	1			T1	14		T13	3		T3	26
valid_sources[0x2b]	11094	1			T1	10		T3	35		T6	7
valid_sources[0x2c]	7661	1			T1	11		T3	25		T6	6
valid_sources[0x2d]	7875	1			T1	7		T13	1		T2	3
valid_sources[0x2e]	13161	1			T1	19		T2	45		T3	17
valid_sources[0x2f]	7135	1			T1	10		T2	48		T3	31
valid_sources[0x30]	11554	1			T1	14		T3	28		T6	12
valid_sources[0x31]	7561	1			T1	9		T2	15		T3	47
valid_sources[0x32]	9205	1			T4	1		T1	4		T2	2
valid_sources[0x33]	8227	1			T1	5		T3	22		T6	4
valid_sources[0x34]	7066	1			T1	10		T3	22		T6	60
valid_sources[0x35]	20337	1			T4	1		T1	12		T2	11
valid_sources[0x36]	7095	1			T1	15		T2	11		T3	21
valid_sources[0x37]	6599	1			T1	9		T2	2		T3	25
valid_sources[0x38]	6997	1			T1	10		T3	29		T6	8
valid_sources[0x39]	8344	1			T1	7		T2	27		T3	53
valid_sources[0x3a]	6824	1			T1	14		T3	21		T6	10
valid_sources[0x3b]	8792	1			T1	7		T5	2		T2	13
valid_sources[0x3c]	15314	1			T1	10		T13	1		T2	2
valid_sources[0x3d]	12668	1			T1	14		T3	31		T6	16
valid_sources[0x3e]	11309	1			T1	11		T3	28		T6	6
valid_sources[0x3f]	6926	1			T1	12		T2	14		T3	12
valid_sources[0x40]	7009	1			T1	20		T2	5		T3	25
valid_sources[0x41]	11312	1			T1	7		T2	28		T3	25
valid_sources[0x42]	11391	1			T1	12		T3	28		T6	8
valid_sources[0x43]	9113	1			T1	14		T2	7		T3	31
valid_sources[0x44]	9673	1			T1	11		T2	11		T3	37
valid_sources[0x45]	10857	1			T1	5		T3	29		T6	18
valid_sources[0x46]	6588	1			T1	12		T5	1		T2	31
valid_sources[0x47]	6986	1			T1	6		T2	13		T3	25
valid_sources[0x48]	7017	1			T1	10		T2	50		T3	30
valid_sources[0x49]	10977	1			T1	6		T2	11		T3	19
valid_sources[0x4a]	7542	1			T4	1		T1	11		T3	18
valid_sources[0x4b]	11591	1			T1	10		T2	21		T3	53
valid_sources[0x4c]	13290	1			T1	13		T3	29		T6	14
valid_sources[0x4d]	6976	1			T1	8		T3	23		T6	4
valid_sources[0x4e]	12131	1			T1	4		T3	17		T6	7
valid_sources[0x4f]	6715	1			T1	6		T2	45		T3	24
valid_sources[0x50]	7021	1			T1	10		T2	4		T3	25
valid_sources[0x51]	7047	1			T1	10		T2	20		T3	40
valid_sources[0x52]	11296	1			T1	13		T2	21		T3	38
valid_sources[0x53]	6827	1			T1	12		T2	4		T3	17
valid_sources[0x54]	6814	1			T1	14		T3	40		T6	6
valid_sources[0x55]	6854	1			T1	6		T2	11		T3	22
valid_sources[0x56]	8294	1			T1	18		T3	22		T6	11
valid_sources[0x57]	6905	1			T1	7		T2	14		T3	27
valid_sources[0x58]	11562	1			T1	5		T2	16		T3	31
valid_sources[0x59]	8928	1			T1	10		T2	7		T3	26
valid_sources[0x5a]	6771	1			T1	15		T3	25		T6	10
valid_sources[0x5b]	7826	1			T1	14		T3	50		T6	5
valid_sources[0x5c]	6900	1			T1	11		T2	31		T3	32
valid_sources[0x5d]	18182	1			T1	8		T3	38		T6	37
valid_sources[0x5e]	7227	1			T1	13		T3	25		T6	3
valid_sources[0x5f]	15676	1			T1	7		T2	7		T3	17
valid_sources[0x60]	8262	1			T1	22		T3	34		T6	3
valid_sources[0x61]	12128	1			T1	8		T2	27		T3	20
valid_sources[0x62]	6881	1			T1	13		T2	19		T3	34
valid_sources[0x63]	7874	1			T1	9		T3	49		T6	25
valid_sources[0x64]	8727	1			T1	19		T3	32		T6	12
valid_sources[0x65]	10038	1			T1	8		T3	27		T6	2
valid_sources[0x66]	7342	1			T1	9		T2	26		T3	24
valid_sources[0x67]	14291	1			T1	5		T2	16		T3	34
valid_sources[0x68]	8186	1			T1	9		T3	23		T6	7
valid_sources[0x69]	6926	1			T1	7		T2	21		T3	43
valid_sources[0x6a]	7654	1			T1	9		T2	17		T3	35
valid_sources[0x6b]	6611	1			T1	15		T3	15		T6	6
valid_sources[0x6c]	7678	1			T1	8		T3	37		T6	8
valid_sources[0x6d]	11870	1			T1	15		T2	27		T3	35
valid_sources[0x6e]	19662	1			T1	9		T3	41		T6	47
valid_sources[0x6f]	8545	1			T1	13		T3	29		T6	8
valid_sources[0x70]	11627	1			T1	6		T2	112		T3	16
valid_sources[0x71]	8436	1			T1	10		T2	48		T3	12
valid_sources[0x72]	6620	1			T1	13		T3	37		T6	5
valid_sources[0x73]	22525	1			T1	13		T2	28		T3	47
valid_sources[0x74]	7352	1			T1	19		T3	13		T6	7
valid_sources[0x75]	6927	1			T1	12		T2	10		T3	38
valid_sources[0x76]	7179	1			T1	11		T2	36		T3	39
valid_sources[0x77]	7228	1			T1	8		T3	31		T6	19
valid_sources[0x78]	7238	1			T1	16		T13	3		T3	19
valid_sources[0x79]	7249	1			T1	12		T2	1		T3	26
valid_sources[0x7a]	6443	1			T1	9		T3	32		T6	51
valid_sources[0x7b]	7354	1			T1	11		T2	10		T3	33
valid_sources[0x7c]	11199	1			T4	1		T1	10		T13	3
valid_sources[0x7d]	8051	1			T1	13		T3	34		T6	34
valid_sources[0x7e]	7205	1			T1	4		T3	21		T6	5
valid_sources[0x7f]	7428	1			T1	16		T2	14		T3	30
valid_sources[0x80]	12143	1			T1	10		T2	6		T3	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1036859

1

T4

1

T1

1196

T5

1

values[0x0]

all_enables

biggest_size

80966

1

T4

2

T1

80

T13

3

values[0x1]

all_enables

biggest_size

58372

1

T4

2

T1

73

T5

1