Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31395	1			T1	20		T2	8		T3	15
auto[PWRUP]	124	1			T63	1		T67	1		T64	3
auto[ONEST_0]	73	1			T64	2		T69	2		T50	1
auto[ONEST_021]	19	1			T64	1		T42	1		T69	1
auto[ONEST_1]	87	1			T63	2		T64	5		T65	3
auto[ONEST_DONE]	1	1			T41	1		-	-		-	-
auto[LP_0]	136	1			T64	3		T65	2		T41	2
auto[LP_021]	27	1			T64	3		T66	1		T41	1
auto[LP_1]	142	1			T63	1		T64	3		T66	2
auto[LP_EVAL]	66	1			T64	1		T65	3		T41	1
auto[LP_SLP]	502	1			T63	4		T67	2		T64	11
auto[LP_PWRUP]	27	1			T63	2		T65	1		T66	1
auto[NP_0]	136	1			T63	2		T67	3		T64	4
auto[NP_021]	34	1			T63	3		T64	1		T65	1
auto[NP_1]	168	1			T63	4		T67	2		T64	6
auto[NP_EVAL]	44	1			T67	1		T202	1		T203	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T204

1

T205

1

T34

1

min

30793

1

T1

20

T2

8

T3

15

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30798	1			T1	20		T2	8		T3	15
pow[0x1]	12	1			T57	1		T206	1		T207	1
pow[0x2]	10	1			T63	1		T41	1		T208	1
pow[0x3]	33	1			T64	3		T66	1		T51	1
pow[0x4]	65	1			T63	2		T64	3		T65	3
pow[0x5]	143	1			T67	1		T64	4		T65	2
pow[0x6]	292	1			T63	2		T67	1		T64	6
pow[0x7]	577	1			T63	4		T67	4		T64	12

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

196

1

T67

1

T64

9

T65

4

min

30315

1

T1

20

T2

8

T3

15

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30316	1			T1	20		T2	8		T3	15
pow[0x4]	2	1			T209	1		T210	1		-	-
pow[0x5]	2	1			T169	1		T211	1		-	-
pow[0x6]	2	1			T57	1		T212	1		-	-
pow[0x7]	3	1			T213	1		T214	1		T215	1
pow[0x8]	4	1			T216	1		T205	1		T171	1
pow[0x9]	8	1			T66	1		T70	1		T206	1
pow[0xa]	18	1			T64	1		T66	1		T71	1
pow[0xb]	35	1			T64	1		T69	1		T53	1
pow[0xc]	85	1			T63	1		T64	3		T65	1
pow[0xd]	175	1			T63	2		T67	2		T64	6
pow[0xe]	302	1			T63	3		T64	10		T65	2
pow[0xf]	619	1			T63	4		T64	15		T65	6