Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2350	1			T5	10		T3	5		T62	2
auto[PWRUP]	152	1			T67	1		T64	8		T66	3
auto[ONEST_0]	92	1			T64	4		T65	1		T66	1
auto[ONEST_021]	30	1			T64	1		T41	1		T69	1
auto[ONEST_1]	88	1			T63	3		T67	1		T64	2
auto[ONEST_DONE]	6	1			T42	1		T347	1		T348	1
auto[LP_0]	134	1			T63	1		T67	2		T64	2
auto[LP_021]	35	1			T64	3		T57	1		T202	1
auto[LP_1]	163	1			T63	1		T67	1		T64	2
auto[LP_EVAL]	58	1			T67	2		T64	2		T65	1
auto[LP_SLP]	558	1			T63	4		T67	5		T64	11
auto[LP_PWRUP]	37	1			T67	1		T71	2		T204	1
auto[NP_0]	214	1			T63	3		T64	3		T65	1
auto[NP_021]	45	1			T64	1		T42	1		T44	1
auto[NP_1]	261	1			T63	3		T64	4		T66	2
auto[NP_EVAL]	28	1			T41	1		T71	1		T204	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T202

1

T349

1

T206

1

min

1969

1

T5

10

T3

5

T62

2

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1992	1			T5	10		T3	5		T62	2
pow[0x1]	13	1			T66	1		T204	1		T350	2
pow[0x2]	14	1			T41	2		T42	1		T203	1
pow[0x3]	42	1			T66	1		T42	1		T69	1
pow[0x4]	77	1			T63	2		T64	2		T69	3
pow[0x5]	140	1			T63	1		T64	5		T65	2
pow[0x6]	288	1			T63	1		T67	5		T64	6
pow[0x7]	530	1			T63	7		T67	2		T64	10

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

199

1

T67

3

T64

3

T65

2

min

1328

1

T5

10

T3

5

T62

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1335	1			T5	10		T3	5		T62	2
pow[0x1]	16	1			T14	1		T48	2		T16	1
pow[0x2]	19	1			T44	1		T15	1		T46	1
pow[0x3]	35	1			T14	4		T46	1		T204	1
pow[0x4]	70	1			T44	3		T45	6		T47	2
pow[0x5]	1	1			T51	1		-	-		-	-
pow[0x6]	1	1			T351	1		-	-		-	-
pow[0x7]	3	1			T207	1		T34	1		T212	1
pow[0x8]	3	1			T204	1		T352	1		T353	1
pow[0x9]	4	1			T208	1		T206	1		T354	1
pow[0xa]	27	1			T64	2		T66	1		T41	1
pow[0xb]	38	1			T64	1		T66	1		T50	1
pow[0xc]	89	1			T63	1		T41	2		T69	1
pow[0xd]	170	1			T63	1		T67	1		T64	7
pow[0xe]	281	1			T63	2		T67	3		T64	6
pow[0xf]	658	1			T63	11		T67	5		T64	17