Unified Coverage Report :: Module :: prim_subreg_arb

Module : prim_subreg_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_ext_0.wr_en_data_arb	0.00	0.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_intr_ext_0.wr_en_data_arb	0.00	0.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_ext_1.wr_en_data_arb	0.00	0.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_intr_ext_1.wr_en_data_arb	0.00	0.00
tb.dut.u_reg.u_intr_state.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_intr_enable.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_en_ctl_adc_enable.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_en_ctl_oneshot_mode.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_pd_ctl_lp_mode.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_pd_ctl_pwrup_time.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_pd_ctl_wakeup_time.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_lp_sample_ctl.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_sample_ctl.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_fsm_rst.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_min_v_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cond_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_max_v_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_en_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_min_v_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cond_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_max_v_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_en_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_min_v_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cond_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_max_v_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_en_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_min_v_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cond_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_max_v_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_en_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_min_v_4.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cond_4.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_max_v_4.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_en_4.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_min_v_5.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cond_5.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_max_v_5.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_en_5.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_min_v_6.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cond_6.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_max_v_6.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_en_6.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_min_v_7.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cond_7.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_max_v_7.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_en_7.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_min_v_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cond_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_max_v_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_en_0.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_min_v_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cond_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_max_v_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_en_1.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_min_v_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cond_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_max_v_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_en_2.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_min_v_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cond_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_max_v_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_en_3.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_min_v_4.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cond_4.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_max_v_4.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_en_4.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_min_v_5.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cond_5.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_max_v_5.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_en_5.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_min_v_6.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cond_6.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_max_v_6.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_en_6.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_min_v_7.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cond_7.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_max_v_7.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_en_7.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_0.wr_en_data_arb	100.00	100.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_intr_0.wr_en_data_arb	100.00	100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_1.wr_en_data_arb	100.00	100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_intr_1.wr_en_data_arb	100.00	100.00
tb.dut.u_reg.u_adc_wakeup_ctl_match_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_wakeup_ctl_trans_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_filter_status_match.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_filter_status_trans.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_intr_ctl_match_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_intr_ctl_trans_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_intr_ctl_oneshot_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_adc_intr_status_match.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_intr_status_trans.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_adc_intr_status_oneshot.wr_en_data_arb	100.00	100.00	100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 + DW=2,SwAccess=1,Mubi=0 + DW=10,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_intr_state.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_ext_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_0.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_intr_ext_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_intr_0.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_ext_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_1.wr_en_data_arb

SCORE	LINE
0.00	0.00

tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_intr_ext_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_intr_1.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	1	1
44	1	1
51		unreachable
52		unreachable
53		unreachable

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=4,SwAccess=0,Mubi=0 + DW=24,SwAccess=0,Mubi=0 + DW=8,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_intr_enable.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_en_ctl_adc_enable.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_en_ctl_oneshot_mode.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_pd_ctl_lp_mode.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_pd_ctl_pwrup_time.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_pd_ctl_wakeup_time.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_lp_sample_ctl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_sample_ctl.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_fsm_rst.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_min_v_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cond_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_max_v_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_en_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_min_v_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cond_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_max_v_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_en_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_min_v_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cond_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_max_v_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_en_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_min_v_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cond_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_max_v_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_en_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_min_v_4.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cond_4.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_max_v_4.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_en_4.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_min_v_5.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cond_5.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_max_v_5.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_en_5.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_min_v_6.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cond_6.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_max_v_6.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_en_6.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_min_v_7.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cond_7.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_max_v_7.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_en_7.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_min_v_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cond_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_max_v_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_en_0.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_min_v_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cond_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_max_v_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_en_1.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_min_v_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cond_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_max_v_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_en_2.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_min_v_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cond_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_max_v_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_en_3.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_min_v_4.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cond_4.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_max_v_4.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_en_4.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_min_v_5.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cond_5.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_max_v_5.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_en_5.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_min_v_6.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cond_6.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_max_v_6.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_en_6.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_min_v_7.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cond_7.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_max_v_7.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_en_7.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_wakeup_ctl_match_en.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_wakeup_ctl_trans_en.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_intr_ctl_match_en.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_intr_ctl_trans_en.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_intr_ctl_oneshot_en.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=3,Mubi=0 + DW=1,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_filter_status_match.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_filter_status_trans.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_intr_status_match.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_intr_status_trans.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_adc_intr_status_oneshot.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_filter_status_match.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_intr_status_match.wr_en_data_arb

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=10,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_min_v_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_max_v_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_min_v_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_max_v_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_min_v_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_max_v_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_min_v_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_max_v_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_min_v_4.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_max_v_4.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_min_v_5.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_max_v_5.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_min_v_6.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_max_v_6.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_min_v_7.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_max_v_7.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_min_v_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_max_v_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_min_v_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_max_v_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_min_v_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_max_v_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_min_v_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_max_v_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_min_v_4.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_max_v_4.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_min_v_5.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_max_v_5.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_min_v_6.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_max_v_6.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_min_v_7.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_max_v_7.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_en_ctl_adc_enable.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_en_ctl_oneshot_mode.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_pd_ctl_lp_mode.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_fsm_rst.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cond_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_en_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cond_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_en_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cond_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_en_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cond_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_en_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cond_4.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_en_4.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cond_5.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_en_5.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cond_6.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_en_6.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cond_7.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_en_7.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cond_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_en_0.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cond_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_en_1.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cond_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_en_2.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cond_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_en_3.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cond_4.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_en_4.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cond_5.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_en_5.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cond_6.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_en_6.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cond_7.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_en_7.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_wakeup_ctl_trans_en.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_intr_ctl_trans_en.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_intr_ctl_oneshot_en.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_filter_status_trans.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_intr_status_trans.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_intr_status_oneshot.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_sample_ctl.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_pd_ctl_pwrup_time.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_lp_sample_ctl.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_wakeup_ctl_match_en.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_intr_ctl_match_en.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=24,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_adc_pd_ctl_wakeup_time.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_subreg_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T5