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Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_chn1_filter_ctl_7_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.73 90.00 66.67 78.26 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.67 94.90 67.39 88.37 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.29 94.12 85.71 83.33 50.00 u_adc_chn_val_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.73 90.00 66.67 78.26 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.67 94.90 67.39 88.37 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.29 94.12 85.71 83.33 50.00 u_adc_chn_val_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_adc_wakeup_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.72 100.00 95.24 95.65 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.79 100.00 93.48 97.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_filter_status_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.58 95.65 78.95 85.71 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.03 97.87 78.57 92.68 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_adc_fsm_state_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00

Go back
Module Instances:
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb
tb.dut.u_reg.u_filter_status_cdc.u_arb
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
283 1 1
284 1 1
299 unreachable


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL504590.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS1216466.67
CONT_ASSIGN13511100.00
ALWAYS13966100.00
ALWAYS15510990.00
CONT_ASSIGN18311100.00
ALWAYS187191789.47
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 0 1
129 1 1
132 0 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 0 1
161 1 1
162 1 1
163 1 1
164 1 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 0 1
203 0 1
204 1 1
205 1 1
206 1 1
207 1 1
210 1 1
211 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb
TotalCoveredPercent
Conditions422866.67
Logical422866.67
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T2,T3

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT4,T1,T5
01Not Covered
10Not Covered

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT4,T1,T5
11CoveredT1,T2,T3

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11Not Covered

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T2,T3

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT4,T1,T5
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT4,T1,T5
10CoveredT1,T2,T3
11Not Covered

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 18 78.26
IF 111 2 2 100.00
IF 121 4 2 50.00
IF 139 4 4 100.00
IF 155 6 5 83.33
CASE 197 7 5 71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 121 if ((!rst_dst_ni)) -2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T1,T5
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T4,T1,T5


LineNo. Expression -1-: 139 if ((!rst_dst_ni)) -2-: 141 if (gen_wr_req.dst_lat_d) -3-: 143 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T1,T5
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T1,T5


LineNo. Expression -1-: 155 if ((!rst_dst_ni)) -2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 163 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T4,T1,T5
0 1 - - - Covered T1,T2,T3
0 0 1 - - Not Covered
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T4,T1,T5


LineNo. Expression -1-: 197 case (gen_wr_req.state_q) -2-: 200 if (gen_wr_req.dst_req) -3-: 204 if (dst_update) -4-: 207 if ((dst_qs_o != dst_qs_i)) -5-: 217 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Not Covered
StIdle 0 1 - - Covered T1,T2,T3
StIdle 0 0 1 - Covered T1,T2,T3
StIdle 0 0 0 - Covered T4,T1,T5
StWait - - - 1 Covered T1,T2,T3
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 34532259 647077 0 918
gen_wr_req.HwIdSelCheck_A 34532259 647247 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34532259 647077 0 918
T1 100559 679 0 1
T2 40180 697 0 1
T3 85098 1443 0 1
T5 849 0 0 1
T6 137714 2080 0 1
T7 96684 2118 0 1
T8 78288 1162 0 1
T9 33173 676 0 1
T10 81088 1387 0 1
T11 0 1411 0 0
T12 0 1371 0 0
T13 94 0 0 1

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34532259 647247 0 0
T1 100559 682 0 0
T2 40180 698 0 0
T3 85098 1444 0 0
T5 849 0 0 0
T6 137714 2080 0 0
T7 96684 2118 0 0
T8 78288 1164 0 0
T9 33173 676 0 0
T10 81088 1387 0 0
T11 0 1411 0 0
T12 0 1371 0 0
T13 94 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL504590.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS1216466.67
CONT_ASSIGN13511100.00
ALWAYS13966100.00
ALWAYS15510990.00
CONT_ASSIGN18311100.00
ALWAYS187191789.47
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 0 1
129 1 1
132 0 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 0 1
161 1 1
162 1 1
163 1 1
164 1 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 0 1
203 0 1
204 1 1
205 1 1
206 1 1
207 1 1
210 1 1
211 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb
TotalCoveredPercent
Conditions422866.67
Logical422866.67
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T2,T3

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT4,T1,T5
01Not Covered
10Not Covered

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT4,T1,T5
11CoveredT1,T2,T3

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11Not Covered

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T2,T3

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT4,T1,T5
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT4,T1,T5
10CoveredT1,T2,T3
11Not Covered

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 18 78.26
IF 111 2 2 100.00
IF 121 4 2 50.00
IF 139 4 4 100.00
IF 155 6 5 83.33
CASE 197 7 5 71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 121 if ((!rst_dst_ni)) -2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T1,T5
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T4,T1,T5


LineNo. Expression -1-: 139 if ((!rst_dst_ni)) -2-: 141 if (gen_wr_req.dst_lat_d) -3-: 143 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T1,T5
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T1,T5


LineNo. Expression -1-: 155 if ((!rst_dst_ni)) -2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 163 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T4,T1,T5
0 1 - - - Covered T1,T2,T3
0 0 1 - - Not Covered
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T4,T1,T5


LineNo. Expression -1-: 197 case (gen_wr_req.state_q) -2-: 200 if (gen_wr_req.dst_req) -3-: 204 if (dst_update) -4-: 207 if ((dst_qs_o != dst_qs_i)) -5-: 217 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Not Covered
StIdle 0 1 - - Covered T1,T2,T3
StIdle 0 0 1 - Covered T1,T2,T3
StIdle 0 0 0 - Covered T4,T1,T5
StWait - - - 1 Covered T1,T2,T3
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 34532259 631903 0 918
gen_wr_req.HwIdSelCheck_A 34532259 639643 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34532259 631903 0 918
T1 100559 662 0 1
T2 40180 672 0 1
T3 85098 1435 0 1
T5 849 0 0 1
T6 137714 2054 0 1
T7 96684 2038 0 1
T8 78288 1130 0 1
T9 33173 690 0 1
T10 81088 1387 0 1
T11 0 1335 0 0
T12 0 1401 0 0
T13 94 0 0 1

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34532259 639643 0 0
T1 100559 668 0 0
T2 40180 682 0 0
T3 85098 1442 0 0
T5 849 0 0 0
T6 137714 2066 0 0
T7 96684 2070 0 0
T8 78288 1140 0 0
T9 33173 695 0 0
T10 81088 1409 0 0
T11 0 1357 0 0
T12 0 1413 0 0
T13 94 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
283 1 1
284 1 1
299 unreachable


Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL5050100.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS12166100.00
CONT_ASSIGN13511100.00
ALWAYS13966100.00
ALWAYS1551010100.00
CONT_ASSIGN18311100.00
ALWAYS1871919100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 1 1
129 1 1
132 1 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
210 1 1
211 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb
TotalCoveredPercent
Conditions424095.24
Logical424095.24
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T8,T58
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T2,T3

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT74,T75,T76
11CoveredT77,T78,T74

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT77,T78,T74

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT1,T2,T3
10CoveredT77,T78,T74

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT74,T75,T76
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT4,T1,T5
11CoveredT1,T2,T3

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01CoveredT77,T78,T74
10CoveredT4,T1,T5
11CoveredT1,T2,T3

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T8,T58

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT4,T1,T5
001CoveredT1,T8,T58
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT4,T1,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 22 95.65
IF 111 2 2 100.00
IF 121 4 4 100.00
IF 139 4 4 100.00
IF 155 6 6 100.00
CASE 197 7 6 85.71

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 121 if ((!rst_dst_ni)) -2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T1,T5
0 1 - Covered T77,T78,T74
0 0 1 Covered T77,T78,T74
0 0 0 Covered T4,T1,T5


LineNo. Expression -1-: 139 if ((!rst_dst_ni)) -2-: 141 if (gen_wr_req.dst_lat_d) -3-: 143 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T1,T5
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T8,T58
0 0 0 Covered T4,T1,T5


LineNo. Expression -1-: 155 if ((!rst_dst_ni)) -2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 163 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T4,T1,T5
0 1 - - - Covered T1,T2,T3
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T8,T58
0 0 0 0 0 Covered T4,T1,T5


LineNo. Expression -1-: 197 case (gen_wr_req.state_q) -2-: 200 if (gen_wr_req.dst_req) -3-: 204 if (dst_update) -4-: 207 if ((dst_qs_o != dst_qs_i)) -5-: 217 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T3
StIdle 0 1 - - Covered T1,T2,T3
StIdle 0 0 1 - Covered T1,T8,T58
StIdle 0 0 0 - Covered T4,T1,T5
StWait - - - 1 Covered T1,T2,T3
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 34532259 14882 0 918
gen_wr_req.HwIdSelCheck_A 34532259 14939 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34532259 14882 0 918
T1 100559 18 0 1
T2 40180 29 0 1
T3 85098 17 0 1
T5 849 0 0 1
T6 137714 29 0 1
T7 96684 44 0 1
T8 78288 20 0 1
T9 33173 8 0 1
T10 81088 52 0 1
T11 0 29 0 0
T12 0 18 0 0
T13 94 0 0 1

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34532259 14939 0 0
T1 100559 19 0 0
T2 40180 29 0 0
T3 85098 17 0 0
T5 849 0 0 0
T6 137714 29 0 0
T7 96684 44 0 0
T8 78288 21 0 0
T9 33173 8 0 0
T10 81088 52 0 0
T11 0 29 0 0
T12 0 18 0 0
T13 94 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL464495.65
CONT_ASSIGN10000
ALWAYS11133100.00
ALWAYS1216466.67
CONT_ASSIGN13511100.00
ALWAYS13966100.00
ALWAYS15599100.00
CONT_ASSIGN18311100.00
ALWAYS1871717100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 0 1
129 1 1
132 0 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 excluded
Exclude Annotation: VC_COV_UNR
163 1 1
164 1 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 unreachable
206 unreachable
207 1 1
210 1 1
211 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb
TotalCoveredPercent
Conditions383078.95
Logical383078.95
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T2,T3

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT44,T45,T14
10Not Covered
11Not Covered

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT44,T45,T14
111Not Covered

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT44,T45,T14
10Not Covered

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Not Covered
11CoveredT44,T45,T14

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT4,T1,T5
11Excluded VC_COV_UNR

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T5
11CoveredT44,T45,T14

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T2,T3

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT4,T1,T5
001CoveredT1,T2,T3
010CoveredT44,T45,T14
100CoveredT1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT4,T1,T5
10CoveredT1,T2,T3
11CoveredT44,T45,T14

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT4,T1,T5

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT44,T45,T14
11CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT4,T1,T5
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb
Line No.TotalCoveredPercent
Branches 21 18 85.71
IF 111 2 2 100.00
IF 121 4 2 50.00
IF 139 4 4 100.00
IF 155 5 5 100.00
CASE 197 6 5 83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T4,T1,T5
0 Covered T4,T1,T5


LineNo. Expression -1-: 121 if ((!rst_dst_ni)) -2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T1,T5
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T4,T1,T5


LineNo. Expression -1-: 139 if ((!rst_dst_ni)) -2-: 141 if (gen_wr_req.dst_lat_d) -3-: 143 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T1,T5
0 1 - Covered T44,T45,T14
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T1,T5


LineNo. Expression -1-: 155 if ((!rst_dst_ni)) -2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 163 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTestsExclude Annotation
1 - - - - Covered T4,T1,T5
0 1 - - - Covered T1,T2,T3
0 0 1 - - Covered T44,T45,T14
0 0 0 1 - Excluded VC_COV_UNR
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T4,T1,T5


LineNo. Expression -1-: 197 case (gen_wr_req.state_q) -2-: 200 if (gen_wr_req.dst_req) -3-: 204 if (dst_update) -4-: 207 if ((dst_qs_o != dst_qs_i)) -5-: 217 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T44,T45,T14
StIdle 0 1 - - Unreachable
StIdle 0 0 1 - Covered T1,T2,T3
StIdle 0 0 0 - Covered T4,T1,T5
StWait - - - 1 Covered T1,T2,T3
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 34532259 0 0 918
gen_wr_req.HwIdSelCheck_A 34532259 3270147 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34532259 0 0 918

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34532259 3270147 0 0
T1 100559 3635 0 0
T2 40180 3901 0 0
T3 85098 8551 0 0
T5 849 0 0 0
T6 137714 13281 0 0
T7 96684 9902 0 0
T8 78288 6655 0 0
T9 33173 3389 0 0
T10 81088 8436 0 0
T11 0 6597 0 0
T12 0 6769 0 0
T13 94 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%