Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1890	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1748	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1735	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1739	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1609	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1727	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1761	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1564	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1637	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1836	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1538	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1691	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1832	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1800	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1758	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1710	0	0
adc_en_ctl_rd_A	2147483647	1251	0	0
adc_fsm_rst_rd_A	2147483647	1135	0	0
adc_intr_ctl_rd_A	2147483647	1898	0	0
adc_lp_sample_ctl_rd_A	2147483647	1098	0	0
adc_pd_ctl_rd_A	2147483647	1552	0	0
adc_sample_ctl_rd_A	2147483647	1087	0	0
adc_wakeup_ctl_rd_A	2147483647	1303	0	0
intr_enable_rd_A	2147483647	1890	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1890	0	0
T14	521172	35	0	0
T15	0	16	0	0
T16	0	33	0	0
T17	0	26	0	0
T18	0	32	0	0
T19	0	17	0	0
T20	0	22	0	0
T21	0	38	0	0
T22	0	30	0	0
T23	0	15	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1748	0	0
T14	521172	51	0	0
T15	0	26	0	0
T16	0	28	0	0
T17	0	11	0	0
T18	0	55	0	0
T19	0	18	0	0
T20	0	13	0	0
T21	0	34	0	0
T22	0	27	0	0
T23	0	15	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1735	0	0
T14	521172	40	0	0
T15	0	20	0	0
T16	0	59	0	0
T17	0	17	0	0
T18	0	42	0	0
T19	0	17	0	0
T20	0	15	0	0
T21	0	31	0	0
T22	0	35	0	0
T23	0	15	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1739	0	0
T14	521172	44	0	0
T15	0	9	0	0
T16	0	44	0	0
T17	0	26	0	0
T18	0	45	0	0
T19	0	26	0	0
T20	0	19	0	0
T21	0	37	0	0
T22	0	35	0	0
T23	0	25	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1609	0	0
T14	521172	36	0	0
T15	0	19	0	0
T16	0	40	0	0
T17	0	28	0	0
T18	0	37	0	0
T19	0	26	0	0
T20	0	14	0	0
T21	0	25	0	0
T22	0	36	0	0
T23	0	26	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1727	0	0
T14	521172	38	0	0
T15	0	16	0	0
T16	0	39	0	0
T17	0	26	0	0
T18	0	36	0	0
T19	0	3	0	0
T20	0	17	0	0
T21	0	28	0	0
T22	0	26	0	0
T23	0	13	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1761	0	0
T14	521172	38	0	0
T15	0	28	0	0
T16	0	33	0	0
T17	0	16	0	0
T18	0	28	0	0
T19	0	23	0	0
T20	0	12	0	0
T21	0	23	0	0
T22	0	39	0	0
T23	0	19	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1564	0	0
T14	521172	34	0	0
T15	0	14	0	0
T16	0	44	0	0
T17	0	16	0	0
T18	0	22	0	0
T19	0	19	0	0
T20	0	17	0	0
T21	0	21	0	0
T22	0	31	0	0
T23	0	26	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1637	0	0
T14	521172	39	0	0
T15	0	11	0	0
T16	0	47	0	0
T17	0	22	0	0
T18	0	45	0	0
T19	0	11	0	0
T20	0	10	0	0
T21	0	28	0	0
T22	0	34	0	0
T23	0	18	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1836	0	0
T14	521172	30	0	0
T15	0	17	0	0
T16	0	50	0	0
T17	0	20	0	0
T18	0	27	0	0
T19	0	11	0	0
T20	0	17	0	0
T21	0	40	0	0
T22	0	54	0	0
T23	0	8	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1538	0	0
T14	521172	23	0	0
T15	0	9	0	0
T16	0	35	0	0
T17	0	28	0	0
T18	0	36	0	0
T19	0	24	0	0
T20	0	8	0	0
T21	0	41	0	0
T22	0	28	0	0
T23	0	25	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1691	0	0
T14	521172	40	0	0
T15	0	20	0	0
T16	0	35	0	0
T17	0	24	0	0
T18	0	19	0	0
T19	0	18	0	0
T20	0	13	0	0
T21	0	40	0	0
T22	0	53	0	0
T23	0	21	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1832	0	0
T14	521172	41	0	0
T15	0	26	0	0
T16	0	51	0	0
T17	0	26	0	0
T18	0	30	0	0
T19	0	22	0	0
T20	0	11	0	0
T21	0	31	0	0
T22	0	36	0	0
T23	0	15	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1800	0	0
T14	521172	46	0	0
T15	0	21	0	0
T16	0	46	0	0
T17	0	22	0	0
T18	0	36	0	0
T19	0	15	0	0
T20	0	16	0	0
T21	0	43	0	0
T22	0	37	0	0
T23	0	9	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1758	0	0
T14	521172	43	0	0
T15	0	11	0	0
T16	0	49	0	0
T17	0	34	0	0
T18	0	41	0	0
T19	0	18	0	0
T20	0	18	0	0
T21	0	40	0	0
T22	0	38	0	0
T23	0	24	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1710	0	0
T14	521172	32	0	0
T15	0	16	0	0
T16	0	39	0	0
T17	0	24	0	0
T18	0	35	0	0
T19	0	18	0	0
T20	0	33	0	0
T21	0	35	0	0
T22	0	24	0	0
T23	0	8	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1251	0	0
T14	521172	37	0	0
T15	0	27	0	0
T16	0	42	0	0
T17	0	26	0	0
T18	0	36	0	0
T19	0	18	0	0
T20	0	14	0	0
T21	0	46	0	0
T22	0	33	0	0
T23	0	22	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1135	0	0
T14	521172	54	0	0
T15	0	30	0	0
T16	0	17	0	0
T17	0	33	0	0
T18	0	42	0	0
T19	0	24	0	0
T20	0	24	0	0
T21	0	41	0	0
T22	0	37	0	0
T23	0	21	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1898	0	0
T14	521172	48	0	0
T15	0	13	0	0
T16	0	31	0	0
T17	0	25	0	0
T18	0	49	0	0
T19	0	23	0	0
T20	0	12	0	0
T21	0	28	0	0
T22	0	49	0	0
T23	0	26	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1098	0	0
T14	521172	36	0	0
T15	0	15	0	0
T16	0	40	0	0
T17	0	33	0	0
T18	0	27	0	0
T19	0	5	0	0
T20	0	10	0	0
T21	0	52	0	0
T22	0	42	0	0
T23	0	17	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1552	0	0
T14	521172	46	0	0
T15	0	17	0	0
T16	0	42	0	0
T17	0	17	0	0
T18	0	35	0	0
T19	0	28	0	0
T20	0	25	0	0
T21	0	22	0	0
T22	0	33	0	0
T23	0	22	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1087	0	0
T14	521172	38	0	0
T15	0	21	0	0
T16	0	33	0	0
T17	0	20	0	0
T18	0	38	0	0
T19	0	15	0	0
T20	0	13	0	0
T21	0	14	0	0
T22	0	44	0	0
T23	0	15	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1303	0	0
T14	521172	30	0	0
T15	0	20	0	0
T16	0	53	0	0
T17	0	15	0	0
T18	0	38	0	0
T19	0	17	0	0
T20	0	21	0	0
T21	0	28	0	0
T22	0	37	0	0
T23	0	11	0	0
T24	153126	0	0	0
T25	26676	0	0	0
T26	116283	0	0	0
T27	329352	0	0	0
T28	594744	0	0	0
T29	47850	0	0	0
T30	143899	0	0	0
T31	120044	0	0	0
T32	328432	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1890	0	0
T14	0	56	0	0
T15	0	23	0	0
T16	0	40	0	0
T17	0	23	0	0
T18	0	46	0	0
T19	0	16	0	0
T20	0	21	0	0
T21	0	63	0	0
T33	827918	17	0	0
T34	0	9	0	0
T35	117289	0	0	0
T36	129328	0	0	0
T37	670936	0	0	0
T38	154424	0	0	0
T39	394992	0	0	0
T40	393423	0	0	0
T41	926710	0	0	0
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