Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1188273	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1161866

1

T1

4321

T2

4248

T3

4164

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2046453	1			T1	8191		T2	8068		T3	8107
values[0x0]	151477	1			T1	338		T2	266		T3	237
values[0x1]	152209	1			T1	343		T2	240		T3	233

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	952251	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1397888

1

T1

5203

T2

5119

T3

5077

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15076	1			T2	33		T3	13		T5	30
valid_sources[0x01]	11323	1			T2	31		T3	6		T5	38
valid_sources[0x02]	7031	1			T2	32		T3	15		T5	36
valid_sources[0x03]	12008	1			T2	35		T3	16		T5	28
valid_sources[0x04]	7340	1			T2	28		T3	19		T5	51
valid_sources[0x05]	6929	1			T2	40		T3	17		T5	18
valid_sources[0x06]	6506	1			T2	27		T3	18		T5	62
valid_sources[0x07]	6986	1			T1	3		T2	49		T3	22
valid_sources[0x08]	7874	1			T2	14		T3	13		T5	24
valid_sources[0x09]	19753	1			T1	1		T2	32		T3	12
valid_sources[0x0a]	24247	1			T2	30		T3	25		T5	45
valid_sources[0x0b]	12989	1			T2	32		T3	13		T5	58
valid_sources[0x0c]	6667	1			T2	34		T3	17		T5	13
valid_sources[0x0d]	14014	1			T2	41		T3	13		T5	36
valid_sources[0x0e]	19950	1			T2	36		T3	22		T5	20
valid_sources[0x0f]	9857	1			T2	37		T3	24		T5	28
valid_sources[0x10]	11040	1			T2	28		T3	15		T5	27
valid_sources[0x11]	10704	1			T2	37		T3	19		T5	48
valid_sources[0x12]	7742	1			T2	44		T3	27		T5	31
valid_sources[0x13]	6463	1			T1	1		T2	33		T3	15
valid_sources[0x14]	7219	1			T1	2		T2	43		T3	26
valid_sources[0x15]	9605	1			T2	25		T3	12		T4	1
valid_sources[0x16]	6886	1			T2	34		T3	27		T5	15
valid_sources[0x17]	11519	1			T2	34		T3	21		T5	39
valid_sources[0x18]	11439	1			T2	32		T3	14		T5	44
valid_sources[0x19]	6738	1			T2	35		T3	18		T5	32
valid_sources[0x1a]	6959	1			T2	44		T3	17		T5	30
valid_sources[0x1b]	9530	1			T2	28		T3	15		T5	28
valid_sources[0x1c]	6886	1			T2	29		T3	20		T4	3
valid_sources[0x1d]	6900	1			T2	45		T3	19		T5	15
valid_sources[0x1e]	12851	1			T2	30		T3	14		T5	46
valid_sources[0x1f]	21440	1			T2	33		T3	15		T5	66
valid_sources[0x20]	7859	1			T2	31		T3	14		T5	18
valid_sources[0x21]	11850	1			T2	34		T3	15		T5	21
valid_sources[0x22]	6899	1			T2	38		T3	17		T5	39
valid_sources[0x23]	6735	1			T2	38		T3	13		T5	42
valid_sources[0x24]	6569	1			T2	33		T3	22		T5	38
valid_sources[0x25]	6867	1			T2	35		T3	12		T5	15
valid_sources[0x26]	11725	1			T1	4298		T2	21		T3	14
valid_sources[0x27]	6522	1			T2	36		T3	20		T5	17
valid_sources[0x28]	10799	1			T2	41		T3	27		T5	30
valid_sources[0x29]	7019	1			T2	26		T3	15		T5	17
valid_sources[0x2a]	10077	1			T2	33		T3	14		T5	27
valid_sources[0x2b]	7805	1			T2	49		T3	29		T5	39
valid_sources[0x2c]	7742	1			T2	37		T3	16		T5	25
valid_sources[0x2d]	6778	1			T2	27		T3	20		T5	41
valid_sources[0x2e]	7867	1			T1	4		T2	39		T3	15
valid_sources[0x2f]	17536	1			T2	24		T3	16		T5	30
valid_sources[0x30]	6649	1			T2	32		T3	17		T5	52
valid_sources[0x31]	12881	1			T2	28		T3	18		T5	33
valid_sources[0x32]	6826	1			T2	32		T3	16		T5	21
valid_sources[0x33]	6656	1			T2	42		T3	14		T5	37
valid_sources[0x34]	7013	1			T2	38		T3	13		T5	50
valid_sources[0x35]	8563	1			T2	28		T3	24		T4	2
valid_sources[0x36]	7226	1			T2	34		T3	19		T5	40
valid_sources[0x37]	6621	1			T2	32		T3	13		T5	33
valid_sources[0x38]	7296	1			T2	27		T3	18		T5	40
valid_sources[0x39]	7629	1			T2	27		T3	19		T5	37
valid_sources[0x3a]	10992	1			T2	35		T3	10		T5	24
valid_sources[0x3b]	6671	1			T2	39		T3	24		T5	27
valid_sources[0x3c]	10745	1			T2	31		T3	29		T5	50
valid_sources[0x3d]	9098	1			T2	32		T3	21		T5	63
valid_sources[0x3e]	11861	1			T2	27		T3	21		T5	20
valid_sources[0x3f]	9451	1			T2	23		T3	16		T5	68
valid_sources[0x40]	10813	1			T1	10		T2	46		T3	11
valid_sources[0x41]	7171	1			T2	31		T3	16		T5	51
valid_sources[0x42]	7616	1			T2	25		T3	16		T5	30
valid_sources[0x43]	7462	1			T2	30		T3	19		T4	3
valid_sources[0x44]	8623	1			T2	40		T3	18		T5	21
valid_sources[0x45]	11338	1			T2	27		T3	13		T5	35
valid_sources[0x46]	18222	1			T2	36		T3	17		T5	81
valid_sources[0x47]	6654	1			T2	27		T3	22		T5	23
valid_sources[0x48]	10780	1			T2	31		T3	19		T5	36
valid_sources[0x49]	15556	1			T2	26		T3	19		T5	39
valid_sources[0x4a]	6492	1			T1	1		T2	29		T3	17
valid_sources[0x4b]	7587	1			T1	1		T2	36		T3	14
valid_sources[0x4c]	6686	1			T2	46		T3	19		T5	52
valid_sources[0x4d]	6830	1			T1	1		T2	26		T3	14
valid_sources[0x4e]	12489	1			T1	1		T2	32		T3	14
valid_sources[0x4f]	6766	1			T2	28		T3	18		T5	18
valid_sources[0x50]	8780	1			T2	31		T3	17		T5	25
valid_sources[0x51]	9314	1			T1	1		T2	35		T3	17
valid_sources[0x52]	7060	1			T2	33		T3	24		T5	24
valid_sources[0x53]	7207	1			T2	36		T3	11		T5	60
valid_sources[0x54]	7971	1			T2	41		T3	15		T5	19
valid_sources[0x55]	7523	1			T1	7		T2	28		T3	25
valid_sources[0x56]	13114	1			T1	2		T2	33		T3	20
valid_sources[0x57]	6776	1			T2	29		T3	19		T5	19
valid_sources[0x58]	7024	1			T2	29		T3	20		T5	33
valid_sources[0x59]	10923	1			T2	45		T3	4266		T5	45
valid_sources[0x5a]	7695	1			T2	33		T3	18		T5	29
valid_sources[0x5b]	6864	1			T2	47		T3	16		T5	23
valid_sources[0x5c]	12365	1			T2	27		T3	18		T5	27
valid_sources[0x5d]	7513	1			T2	44		T3	20		T5	42
valid_sources[0x5e]	7553	1			T2	32		T3	15		T5	27
valid_sources[0x5f]	9099	1			T2	36		T3	21		T5	30
valid_sources[0x60]	7272	1			T2	34		T3	14		T5	43
valid_sources[0x61]	10967	1			T2	29		T3	11		T5	51
valid_sources[0x62]	6902	1			T1	5		T2	38		T3	11
valid_sources[0x63]	7008	1			T2	31		T3	16		T5	19
valid_sources[0x64]	6834	1			T2	31		T3	16		T5	43
valid_sources[0x65]	7845	1			T1	2		T2	26		T3	9
valid_sources[0x66]	9830	1			T2	27		T3	9		T5	43
valid_sources[0x67]	11247	1			T1	2		T2	40		T3	17
valid_sources[0x68]	6734	1			T2	30		T3	16		T4	1
valid_sources[0x69]	7511	1			T2	29		T3	24		T5	15
valid_sources[0x6a]	21073	1			T2	30		T3	19		T5	19
valid_sources[0x6b]	9934	1			T2	31		T3	22		T5	21
valid_sources[0x6c]	7482	1			T2	33		T3	17		T5	52
valid_sources[0x6d]	8852	1			T2	26		T3	19		T5	24
valid_sources[0x6e]	6839	1			T2	38		T3	14		T5	14
valid_sources[0x6f]	6970	1			T1	1		T2	35		T3	27
valid_sources[0x70]	9636	1			T2	32		T3	24		T5	20
valid_sources[0x71]	7044	1			T2	34		T3	15		T5	45
valid_sources[0x72]	6864	1			T2	22		T3	16		T5	23
valid_sources[0x73]	6893	1			T2	27		T3	24		T12	19
valid_sources[0x74]	6643	1			T2	43		T3	16		T5	22
valid_sources[0x75]	8075	1			T2	31		T3	16		T5	34
valid_sources[0x76]	7011	1			T2	30		T3	20		T5	49
valid_sources[0x77]	6800	1			T2	33		T3	21		T5	12
valid_sources[0x78]	8657	1			T2	43		T3	18		T5	42
valid_sources[0x79]	11291	1			T2	33		T3	15		T5	52
valid_sources[0x7a]	7003	1			T2	38		T3	14		T5	32
valid_sources[0x7b]	7155	1			T2	31		T3	16		T5	22
valid_sources[0x7c]	12044	1			T2	28		T3	21		T5	23
valid_sources[0x7d]	6647	1			T2	45		T3	11		T5	27
valid_sources[0x7e]	11210	1			T2	20		T3	20		T5	19
valid_sources[0x7f]	11346	1			T1	2		T2	38		T3	19
valid_sources[0x80]	6495	1			T2	38		T3	13		T4	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1018886

1

T1

4054

T2

4060

T3

3974

values[0x0]

all_enables

biggest_size

82952

1

T1

149

T2

128

T3

123

values[0x1]

all_enables

biggest_size

60028

1

T1

118

T2

60

T3

67