Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	32442	1			T1	16		T2	11		T3	15
auto[PWRUP]	101	1			T9	1		T24	1		T32	2
auto[ONEST_0]	78	1			T9	1		T32	1		T40	1
auto[ONEST_021]	23	1			T41	1		T182	1		T183	1
auto[ONEST_1]	76	1			T24	1		T32	1		T41	2
auto[ONEST_DONE]	3	1			T184	1		T185	1		T186	1
auto[LP_0]	146	1			T9	1		T32	1		T181	1
auto[LP_021]	26	1			T32	1		T35	2		T36	2
auto[LP_1]	163	1			T9	3		T24	3		T40	1
auto[LP_EVAL]	67	1			T8	4		T24	3		T40	1
auto[LP_SLP]	534	1			T8	2		T9	4		T24	4
auto[LP_PWRUP]	28	1			T24	1		T32	1		T187	1
auto[NP_0]	176	1			T8	2		T9	4		T24	1
auto[NP_021]	37	1			T24	2		T32	1		T40	1
auto[NP_1]	170	1			T9	1		T24	1		T40	1
auto[NP_EVAL]	33	1			T36	1		T37	1		T184	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T24

1

T32

1

T188

1

min

31837

1

T1

16

T2

11

T3

15

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	31846	1			T1	16		T2	11		T3	15
pow[0x1]	6	1			T39	2		T183	1		T189	1
pow[0x2]	18	1			T24	1		T36	1		T37	1
pow[0x3]	26	1			T9	2		T24	1		T184	1
pow[0x4]	77	1			T8	2		T9	1		T24	1
pow[0x5]	138	1			T9	1		T32	1		T40	2
pow[0x6]	287	1			T8	1		T9	1		T24	1
pow[0x7]	565	1			T8	3		T9	5		T24	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

209

1

T8

1

T24

1

T32

4

min

31315

1

T1

16

T2

11

T3

15

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	31315	1			T1	16		T2	11		T3	15
pow[0x2]	1	1			T190	1		-	-		-	-
pow[0x6]	3	1			T191	1		T25	1		T192	1
pow[0x7]	2	1			T193	1		T194	1		-	-
pow[0x8]	4	1			T194	1		T195	1		T196	1
pow[0x9]	10	1			T41	1		T184	1		T39	1
pow[0xa]	24	1			T24	1		T35	1		T184	1
pow[0xb]	53	1			T24	1		T35	1		T37	1
pow[0xc]	86	1			T24	2		T40	2		T181	1
pow[0xd]	157	1			T8	1		T24	1		T40	1
pow[0xe]	316	1			T8	2		T9	2		T24	5
pow[0xf]	610	1			T8	4		T9	7		T24	3