Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2388	1			T1	5		T5	4		T6	6
auto[PWRUP]	136	1			T8	1		T9	1		T24	2
auto[ONEST_0]	82	1			T24	1		T32	1		T40	2
auto[ONEST_021]	19	1			T32	1		T40	1		T184	1
auto[ONEST_1]	81	1			T9	1		T24	1		T181	1
auto[ONEST_DONE]	5	1			T9	1		T347	1		T186	1
auto[LP_0]	136	1			T8	1		T9	3		T32	2
auto[LP_021]	37	1			T32	1		T212	1		T182	3
auto[LP_1]	164	1			T6	1		T9	4		T24	2
auto[LP_EVAL]	47	1			T6	1		T9	1		T24	1
auto[LP_SLP]	587	1			T8	6		T9	5		T24	3
auto[LP_PWRUP]	28	1			T9	1		T32	1		T181	1
auto[NP_0]	222	1			T8	1		T9	3		T24	2
auto[NP_021]	47	1			T6	1		T181	1		T35	1
auto[NP_1]	255	1			T6	1		T8	1		T9	2
auto[NP_EVAL]	38	1			T9	3		T40	1		T181	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

12

1

T35

1

T193

1

T18

1

min

2020

1

T1

5

T5

4

T6

7

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2038	1			T1	5		T5	4		T6	7
pow[0x1]	9	1			T13	1		T184	1		T189	1
pow[0x2]	22	1			T184	1		T183	1		T348	1
pow[0x3]	31	1			T6	1		T40	1		T41	2
pow[0x4]	71	1			T9	1		T181	1		T13	1
pow[0x5]	127	1			T9	5		T24	1		T32	2
pow[0x6]	308	1			T8	1		T9	3		T24	4
pow[0x7]	570	1			T6	2		T8	3		T9	9

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

216

1

T9

3

T32

4

T40

4

min

1360

1

T1

5

T5

4

T6

6

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1370	1			T1	5		T5	4		T6	6
pow[0x1]	20	1			T24	1		T29	5		T16	3
pow[0x2]	20	1			T6	1		T14	5		T247	3
pow[0x3]	38	1			T6	1		T9	2		T30	3
pow[0x4]	60	1			T8	1		T9	2		T24	1
pow[0x5]	2	1			T315	1		T349	1		-	-
pow[0x7]	3	1			T188	1		T350	1		T351	1
pow[0x8]	2	1			T181	1		T352	1		-	-
pow[0x9]	13	1			T32	1		T350	1		T353	2
pow[0xa]	20	1			T9	1		T32	1		T41	1
pow[0xb]	40	1			T24	1		T40	1		T41	2
pow[0xc]	70	1			T24	1		T32	1		T40	2
pow[0xd]	159	1			T8	1		T9	3		T24	1
pow[0xe]	337	1			T8	3		T9	2		T24	1
pow[0xf]	601	1			T8	2		T9	6		T24	7