Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1125568	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1097837

1

T1

1427

T2

23

T3

2093

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1938855	1			T1	2586		T3	4061		T4	838
values[0x0]	141586	1			T1	165		T2	20		T3	127
values[0x1]	142964	1			T1	153		T2	23		T3	135

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	901317	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1322088

1

T1

1712

T2

26

T3

2524

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6680	1			T3	14		T4	2		T5	55
valid_sources[0x01]	6682	1			T3	13		T4	3		T5	71
valid_sources[0x02]	6677	1			T3	14		T4	3		T5	51
valid_sources[0x03]	15591	1			T3	20		T4	3		T5	71
valid_sources[0x04]	6953	1			T3	19		T4	7		T5	51
valid_sources[0x05]	16582	1			T3	25		T4	3		T5	19
valid_sources[0x06]	15226	1			T1	2904		T2	1		T3	16
valid_sources[0x07]	6852	1			T3	16		T4	4		T5	62
valid_sources[0x08]	6591	1			T3	9		T4	4		T5	42
valid_sources[0x09]	6409	1			T3	20		T4	3		T5	50
valid_sources[0x0a]	7690	1			T3	13		T4	3		T5	52
valid_sources[0x0b]	10175	1			T3	19		T4	2		T5	33
valid_sources[0x0c]	6618	1			T3	11		T4	2		T5	24
valid_sources[0x0d]	8934	1			T2	1		T3	6		T4	4
valid_sources[0x0e]	11250	1			T3	25		T4	3		T5	26
valid_sources[0x0f]	6546	1			T3	16		T4	3		T5	74
valid_sources[0x10]	10959	1			T3	12		T4	7		T5	73
valid_sources[0x11]	7572	1			T3	29		T4	1		T5	74
valid_sources[0x12]	11487	1			T3	20		T4	5		T5	41
valid_sources[0x13]	7553	1			T3	26		T4	6		T5	61
valid_sources[0x14]	11325	1			T3	8		T4	1		T5	75
valid_sources[0x15]	16291	1			T2	2		T3	18		T4	3
valid_sources[0x16]	7612	1			T3	19		T4	2		T5	32
valid_sources[0x17]	8762	1			T2	2		T3	16		T4	3
valid_sources[0x18]	7053	1			T3	16		T4	2		T5	62
valid_sources[0x19]	6505	1			T3	16		T4	3		T5	53
valid_sources[0x1a]	6426	1			T3	16		T4	2		T5	44
valid_sources[0x1b]	11081	1			T3	22		T4	2		T5	47
valid_sources[0x1c]	7039	1			T3	25		T4	5		T5	32
valid_sources[0x1d]	7385	1			T3	8		T4	4		T5	70
valid_sources[0x1e]	6407	1			T3	5		T4	3		T5	29
valid_sources[0x1f]	11331	1			T3	24		T4	6		T5	55
valid_sources[0x20]	6553	1			T3	13		T4	2		T5	33
valid_sources[0x21]	7369	1			T3	15		T4	8		T5	61
valid_sources[0x22]	13256	1			T3	9		T4	2		T5	25
valid_sources[0x23]	10383	1			T3	12		T4	7		T5	99
valid_sources[0x24]	6898	1			T3	28		T4	5		T5	59
valid_sources[0x25]	6797	1			T3	23		T4	3		T5	32
valid_sources[0x26]	6804	1			T3	13		T4	2		T5	32
valid_sources[0x27]	6922	1			T3	16		T4	4		T5	45
valid_sources[0x28]	6487	1			T3	24		T4	2		T5	63
valid_sources[0x29]	13030	1			T3	30		T4	6		T5	52
valid_sources[0x2a]	6592	1			T3	17		T4	1		T5	50
valid_sources[0x2b]	9592	1			T3	13		T4	3		T5	46
valid_sources[0x2c]	6725	1			T3	26		T4	5		T5	48
valid_sources[0x2d]	11341	1			T3	22		T5	75		T6	12
valid_sources[0x2e]	7268	1			T3	7		T4	8		T5	32
valid_sources[0x2f]	7521	1			T3	10		T4	5		T5	54
valid_sources[0x30]	7962	1			T3	11		T4	3		T5	58
valid_sources[0x31]	8096	1			T3	18		T4	4		T5	50
valid_sources[0x32]	11755	1			T3	15		T4	4		T5	72
valid_sources[0x33]	11309	1			T3	13		T4	6		T5	36
valid_sources[0x34]	6427	1			T3	18		T4	2		T5	51
valid_sources[0x35]	9379	1			T2	1		T3	12		T4	4
valid_sources[0x36]	6292	1			T3	17		T4	2		T5	47
valid_sources[0x37]	6374	1			T3	6		T4	3		T5	43
valid_sources[0x38]	7782	1			T3	18		T4	1		T5	38
valid_sources[0x39]	8198	1			T2	1		T3	10		T4	3
valid_sources[0x3a]	10038	1			T3	26		T4	5		T5	53
valid_sources[0x3b]	6582	1			T3	13		T4	3		T5	31
valid_sources[0x3c]	6500	1			T3	23		T4	4		T5	45
valid_sources[0x3d]	7397	1			T3	17		T4	5		T5	64
valid_sources[0x3e]	6606	1			T3	21		T4	3		T5	51
valid_sources[0x3f]	15157	1			T3	20		T4	4		T5	61
valid_sources[0x40]	6551	1			T3	23		T4	5		T5	81
valid_sources[0x41]	10510	1			T3	27		T4	5		T5	36
valid_sources[0x42]	9301	1			T3	15		T4	4		T5	68
valid_sources[0x43]	7834	1			T2	1		T3	2		T4	3
valid_sources[0x44]	6895	1			T3	14		T4	2		T5	80
valid_sources[0x45]	23950	1			T3	17		T4	1		T5	18
valid_sources[0x46]	8607	1			T3	15		T4	5		T5	48
valid_sources[0x47]	11122	1			T3	9		T4	5		T5	77
valid_sources[0x48]	11007	1			T3	16		T4	2		T5	83
valid_sources[0x49]	8689	1			T3	13		T4	2		T5	44
valid_sources[0x4a]	11030	1			T3	30		T4	3		T5	57
valid_sources[0x4b]	11312	1			T3	19		T4	5		T5	18
valid_sources[0x4c]	7842	1			T3	13		T4	7		T5	40
valid_sources[0x4d]	7822	1			T3	14		T4	3		T5	57
valid_sources[0x4e]	6749	1			T3	26		T4	1		T5	26
valid_sources[0x4f]	6476	1			T3	14		T4	2		T5	44
valid_sources[0x50]	8994	1			T3	11		T4	2		T5	50
valid_sources[0x51]	7762	1			T3	13		T4	1		T5	64
valid_sources[0x52]	6644	1			T3	17		T4	4		T5	69
valid_sources[0x53]	7105	1			T3	17		T4	3		T5	47
valid_sources[0x54]	9472	1			T3	15		T4	6		T5	54
valid_sources[0x55]	7092	1			T3	16		T4	4		T5	32
valid_sources[0x56]	7885	1			T2	1		T3	13		T4	3
valid_sources[0x57]	10950	1			T2	1		T3	24		T4	2
valid_sources[0x58]	9761	1			T3	11		T4	2		T5	73
valid_sources[0x59]	7341	1			T3	23		T4	4		T5	35
valid_sources[0x5a]	7403	1			T3	15		T4	6		T5	38
valid_sources[0x5b]	7733	1			T2	1		T3	21		T4	6
valid_sources[0x5c]	7692	1			T3	14		T4	6		T5	70
valid_sources[0x5d]	6716	1			T2	2		T3	15		T4	2
valid_sources[0x5e]	6538	1			T2	1		T3	18		T4	1
valid_sources[0x5f]	9853	1			T3	8		T4	5		T5	57
valid_sources[0x60]	6727	1			T3	17		T4	7		T5	34
valid_sources[0x61]	8110	1			T3	21		T4	4		T5	36
valid_sources[0x62]	10983	1			T3	16		T4	2		T5	49
valid_sources[0x63]	6460	1			T3	14		T4	4		T5	48
valid_sources[0x64]	7630	1			T2	2		T3	17		T4	2
valid_sources[0x65]	7279	1			T3	20		T4	7		T5	74
valid_sources[0x66]	9825	1			T2	1		T3	32		T4	3
valid_sources[0x67]	6740	1			T2	3		T3	15		T4	8
valid_sources[0x68]	6323	1			T3	19		T4	3		T5	77
valid_sources[0x69]	7873	1			T3	15		T5	49		T6	11
valid_sources[0x6a]	9444	1			T3	12		T4	6		T5	63
valid_sources[0x6b]	10437	1			T3	13		T4	7		T5	52
valid_sources[0x6c]	6831	1			T3	23		T4	2		T5	51
valid_sources[0x6d]	7207	1			T3	16		T4	4		T5	59
valid_sources[0x6e]	10819	1			T3	23		T4	2		T5	28
valid_sources[0x6f]	6514	1			T3	26		T4	4		T5	50
valid_sources[0x70]	6767	1			T2	1		T3	14		T4	4
valid_sources[0x71]	7095	1			T3	15		T4	4		T5	72
valid_sources[0x72]	7022	1			T3	29		T4	4		T5	123
valid_sources[0x73]	7787	1			T3	11		T4	2		T5	37
valid_sources[0x74]	10655	1			T3	21		T4	3		T5	45
valid_sources[0x75]	8878	1			T3	16		T4	3		T5	46
valid_sources[0x76]	10381	1			T3	21		T4	1		T5	39
valid_sources[0x77]	11084	1			T3	11		T4	2		T5	52
valid_sources[0x78]	7263	1			T3	19		T4	8		T5	50
valid_sources[0x79]	12186	1			T3	10		T4	4		T5	46
valid_sources[0x7a]	6670	1			T3	12		T4	1		T5	53
valid_sources[0x7b]	6759	1			T3	14		T4	7		T5	41
valid_sources[0x7c]	6613	1			T2	1		T3	12		T4	2
valid_sources[0x7d]	6377	1			T3	15		T4	8		T5	43
valid_sources[0x7e]	7603	1			T3	5		T4	5		T5	45
valid_sources[0x7f]	7735	1			T3	31		T4	7		T5	58
valid_sources[0x80]	6583	1			T3	18		T4	4		T5	49

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

964663

1

T1

1280

T3

2000

T4

430

values[0x0]

all_enables

biggest_size

77252

1

T1

86

T2

11

T3

57

values[0x1]

all_enables

biggest_size

55922

1

T1

61

T2

12

T3

36