Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28145	1			T1	25		T3	9		T4	6
auto[PWRUP]	116	1			T12	1		T53	1		T54	3
auto[ONEST_0]	77	1			T12	3		T23	2		T54	2
auto[ONEST_021]	21	1			T12	1		T54	2		T56	1
auto[ONEST_1]	85	1			T12	1		T23	1		T53	1
auto[ONEST_DONE]	8	1			T12	1		T54	1		T214	1
auto[LP_0]	123	1			T12	1		T53	3		T54	4
auto[LP_021]	37	1			T54	1		T57	1		T45	3
auto[LP_1]	133	1			T23	1		T53	3		T54	3
auto[LP_EVAL]	61	1			T40	1		T53	3		T173	2
auto[LP_SLP]	472	1			T12	3		T23	4		T53	6
auto[LP_PWRUP]	29	1			T23	1		T53	1		T56	1
auto[NP_0]	176	1			T12	3		T40	1		T53	3
auto[NP_021]	35	1			T53	1		T41	1		T56	1
auto[NP_1]	176	1			T12	2		T40	1		T23	2
auto[NP_EVAL]	42	1			T23	1		T53	1		T43	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T43

1

T215

1

T216

1

min

27570

1

T1

25

T3

9

T4

6

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27577	1			T1	25		T3	9		T4	6
pow[0x1]	10	1			T54	1		T43	1		T122	1
pow[0x2]	20	1			T12	1		T54	1		T56	2
pow[0x3]	32	1			T54	1		T41	1		T55	1
pow[0x4]	58	1			T12	2		T54	1		T177	1
pow[0x5]	142	1			T12	1		T40	1		T54	2
pow[0x6]	273	1			T12	1		T23	3		T53	4
pow[0x7]	524	1			T12	8		T13	1		T23	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

199

1

T12

1

T13

1

T53

3

min

27127

1

T1

25

T3

9

T4

6

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27127	1			T1	25		T3	9		T4	6
pow[0x2]	1	1			T54	1		-	-		-	-
pow[0x5]	1	1			T217	1		-	-		-	-
pow[0x7]	2	1			T218	1		T219	1		-	-
pow[0x8]	5	1			T219	1		T34	1		T220	1
pow[0x9]	13	1			T53	1		T176	1		T219	1
pow[0xa]	15	1			T41	1		T176	1		T221	1
pow[0xb]	35	1			T173	1		T218	1		T177	1
pow[0xc]	91	1			T23	2		T53	3		T54	1
pow[0xd]	156	1			T12	3		T53	1		T54	1
pow[0xe]	301	1			T12	4		T23	2		T53	3
pow[0xf]	608	1			T12	4		T23	4		T53	8