Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2349	1			T8	5		T12	26		T40	7
auto[PWRUP]	132	1			T13	1		T53	1		T54	3
auto[ONEST_0]	77	1			T12	1		T54	1		T173	1
auto[ONEST_021]	23	1			T54	1		T45	1		T331	1
auto[ONEST_1]	107	1			T12	1		T40	1		T53	2
auto[ONEST_DONE]	3	1			T332	1		T333	1		T216	1
auto[LP_0]	118	1			T54	1		T41	1		T55	2
auto[LP_021]	35	1			T12	1		T55	1		T176	1
auto[LP_1]	143	1			T12	2		T40	1		T13	2
auto[LP_EVAL]	66	1			T12	2		T13	1		T53	2
auto[LP_SLP]	539	1			T12	6		T40	1		T13	1
auto[LP_PWRUP]	28	1			T23	1		T57	2		T218	1
auto[NP_0]	236	1			T12	5		T40	1		T13	2
auto[NP_021]	50	1			T12	1		T55	1		T56	1
auto[NP_1]	210	1			T12	1		T40	1		T13	1
auto[NP_EVAL]	35	1			T12	1		T54	1		T56	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T56

1

T334

1

T335

1

min

1998

1

T8

5

T12

11

T40

11

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2014	1			T8	5		T12	11		T40	11
pow[0x1]	13	1			T12	1		T53	1		T221	1
pow[0x2]	13	1			T55	1		T44	1		T332	1
pow[0x3]	30	1			T54	1		T218	1		T221	1
pow[0x4]	67	1			T23	1		T53	1		T173	3
pow[0x5]	129	1			T12	5		T53	3		T54	1
pow[0x6]	271	1			T12	7		T13	1		T23	1
pow[0x7]	493	1			T12	8		T23	2		T53	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

191

1

T12

3

T23

2

T53

2

min

1382

1

T8

5

T12

6

T40

7

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1389	1			T8	5		T12	6		T40	7
pow[0x1]	5	1			T42	2		T265	1		T284	1
pow[0x2]	16	1			T43	1		T50	1		T51	1
pow[0x3]	46	1			T40	2		T13	1		T42	1
pow[0x4]	69	1			T41	2		T44	2		T45	2
pow[0x5]	2	1			T336	1		T282	1		-	-
pow[0x6]	2	1			T337	1		T338	1		-	-
pow[0x7]	3	1			T217	2		T281	1		-	-
pow[0x8]	7	1			T53	1		T177	1		T215	1
pow[0x9]	10	1			T332	1		T123	1		T339	1
pow[0xa]	18	1			T12	1		T54	1		T57	1
pow[0xb]	56	1			T12	2		T54	2		T57	2
pow[0xc]	76	1			T53	1		T173	1		T41	1
pow[0xd]	166	1			T12	4		T23	2		T53	3
pow[0xe]	290	1			T12	5		T23	1		T53	1
pow[0xf]	577	1			T12	8		T40	1		T13	1