Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : adc_ctrl_fsm_sva
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva 100.00 100.00



Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.75 100.00 100.00 100.00 98.73 100.00 u_adc_ctrl_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : adc_ctrl_fsm_sva
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 11 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 11 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FsmDebugOut_A 31110514 31030468 0 0
FsmStateHwReset_A 1157 1157 0 0
FsmStateSwReset_A 31110514 6081 0 0
LpSampleCntHwReset_A 1157 1157 0 0
LpSampleCntSwReset_A 31110514 6081 0 0
NpSampleCntHwReset_A 1157 1157 0 0
NpSampleCntSwReset_A 31110514 6081 0 0
PwrupTimerCntHwReset_A 1157 1157 0 0
PwrupTimerCntSwReset_A 31110514 6081 0 0
WakeupTimerCntHwReset_A 1157 1157 0 0
WakeupTimerCntSwReset_A 31110514 6081 0 0


FsmDebugOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 31110514 31030468 0 0
T1 101115 101020 0 0
T2 6313 6241 0 0
T3 32905 32845 0 0
T4 32718 32663 0 0
T5 109536 109486 0 0
T6 66427 66372 0 0
T7 34131 34075 0 0
T8 72127 71677 0 0
T9 1153 1062 0 0
T10 56143 56044 0 0

FsmStateHwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1157 1157 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 6 6 0 0
T9 1 1 0 0
T10 1 1 0 0

FsmStateSwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 31110514 6081 0 0
T1 101115 25 0 0
T2 6313 0 0 0
T3 32905 9 0 0
T4 32718 6 0 0
T5 109536 19 0 0
T6 66427 16 0 0
T7 34131 10 0 0
T8 72127 18 0 0
T9 1153 0 0 0
T10 56143 6 0 0
T11 0 20 0 0
T12 0 9 0 0

LpSampleCntHwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1157 1157 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 6 6 0 0
T9 1 1 0 0
T10 1 1 0 0

LpSampleCntSwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 31110514 6081 0 0
T1 101115 25 0 0
T2 6313 0 0 0
T3 32905 9 0 0
T4 32718 6 0 0
T5 109536 19 0 0
T6 66427 16 0 0
T7 34131 10 0 0
T8 72127 18 0 0
T9 1153 0 0 0
T10 56143 6 0 0
T11 0 20 0 0
T12 0 9 0 0

NpSampleCntHwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1157 1157 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 6 6 0 0
T9 1 1 0 0
T10 1 1 0 0

NpSampleCntSwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 31110514 6081 0 0
T1 101115 25 0 0
T2 6313 0 0 0
T3 32905 9 0 0
T4 32718 6 0 0
T5 109536 19 0 0
T6 66427 16 0 0
T7 34131 10 0 0
T8 72127 18 0 0
T9 1153 0 0 0
T10 56143 6 0 0
T11 0 20 0 0
T12 0 9 0 0

PwrupTimerCntHwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1157 1157 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 6 6 0 0
T9 1 1 0 0
T10 1 1 0 0

PwrupTimerCntSwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 31110514 6081 0 0
T1 101115 25 0 0
T2 6313 0 0 0
T3 32905 9 0 0
T4 32718 6 0 0
T5 109536 19 0 0
T6 66427 16 0 0
T7 34131 10 0 0
T8 72127 18 0 0
T9 1153 0 0 0
T10 56143 6 0 0
T11 0 20 0 0
T12 0 9 0 0

WakeupTimerCntHwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1157 1157 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 6 6 0 0
T9 1 1 0 0
T10 1 1 0 0

WakeupTimerCntSwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 31110514 6081 0 0
T1 101115 25 0 0
T2 6313 0 0 0
T3 32905 9 0 0
T4 32718 6 0 0
T5 109536 19 0 0
T6 66427 16 0 0
T7 34131 10 0 0
T8 72127 18 0 0
T9 1153 0 0 0
T10 56143 6 0 0
T11 0 20 0 0
T12 0 9 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%