Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1567	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1697	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1460	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1529	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1627	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1611	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1523	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1716	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1760	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1762	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1673	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1575	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1683	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1663	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1613	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1564	0	0
adc_en_ctl_rd_A	2147483647	1397	0	0
adc_fsm_rst_rd_A	2147483647	1066	0	0
adc_intr_ctl_rd_A	2147483647	1695	0	0
adc_lp_sample_ctl_rd_A	2147483647	1146	0	0
adc_pd_ctl_rd_A	2147483647	1397	0	0
adc_sample_ctl_rd_A	2147483647	1120	0	0
adc_wakeup_ctl_rd_A	2147483647	1308	0	0
intr_enable_rd_A	2147483647	1790	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1567	0	0
T13	251007	32	0	0
T14	0	6	0	0
T15	0	1	0	0
T16	0	20	0	0
T17	0	16	0	0
T18	0	52	0	0
T19	0	35	0	0
T20	0	17	0	0
T21	0	27	0	0
T22	0	36	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1697	0	0
T13	251007	40	0	0
T14	0	27	0	0
T15	0	3	0	0
T16	0	22	0	0
T17	0	20	0	0
T18	0	29	0	0
T19	0	26	0	0
T20	0	21	0	0
T21	0	24	0	0
T22	0	41	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1460	0	0
T13	251007	41	0	0
T14	0	3	0	0
T16	0	9	0	0
T17	0	19	0	0
T18	0	24	0	0
T19	0	21	0	0
T20	0	12	0	0
T21	0	28	0	0
T22	0	32	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0
T32	0	11	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1529	0	0
T13	251007	45	0	0
T14	0	11	0	0
T15	0	13	0	0
T16	0	21	0	0
T17	0	17	0	0
T18	0	26	0	0
T19	0	26	0	0
T20	0	20	0	0
T21	0	23	0	0
T22	0	27	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1627	0	0
T13	251007	39	0	0
T14	0	23	0	0
T15	0	6	0	0
T16	0	20	0	0
T17	0	23	0	0
T18	0	28	0	0
T19	0	13	0	0
T20	0	31	0	0
T21	0	18	0	0
T22	0	19	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1611	0	0
T13	251007	41	0	0
T14	0	18	0	0
T15	0	6	0	0
T16	0	14	0	0
T17	0	19	0	0
T18	0	43	0	0
T19	0	5	0	0
T20	0	14	0	0
T21	0	8	0	0
T22	0	42	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1523	0	0
T13	251007	42	0	0
T14	0	7	0	0
T15	0	13	0	0
T16	0	26	0	0
T17	0	24	0	0
T18	0	42	0	0
T19	0	42	0	0
T20	0	19	0	0
T21	0	22	0	0
T22	0	38	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1716	0	0
T13	251007	28	0	0
T14	0	16	0	0
T15	0	18	0	0
T16	0	16	0	0
T17	0	22	0	0
T18	0	34	0	0
T19	0	1	0	0
T20	0	14	0	0
T21	0	19	0	0
T22	0	26	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1760	0	0
T13	251007	48	0	0
T14	0	19	0	0
T15	0	4	0	0
T16	0	25	0	0
T17	0	20	0	0
T18	0	39	0	0
T19	0	23	0	0
T20	0	24	0	0
T21	0	20	0	0
T22	0	42	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1762	0	0
T13	251007	19	0	0
T14	0	25	0	0
T15	0	7	0	0
T16	0	17	0	0
T17	0	18	0	0
T18	0	34	0	0
T19	0	20	0	0
T20	0	21	0	0
T21	0	16	0	0
T22	0	41	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1673	0	0
T13	251007	46	0	0
T14	0	14	0	0
T15	0	5	0	0
T16	0	22	0	0
T17	0	26	0	0
T18	0	45	0	0
T19	0	9	0	0
T20	0	23	0	0
T21	0	23	0	0
T22	0	46	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1575	0	0
T13	251007	51	0	0
T14	0	4	0	0
T15	0	14	0	0
T16	0	26	0	0
T17	0	15	0	0
T18	0	35	0	0
T19	0	21	0	0
T20	0	24	0	0
T21	0	17	0	0
T22	0	21	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1683	0	0
T13	251007	39	0	0
T14	0	20	0	0
T15	0	12	0	0
T16	0	14	0	0
T17	0	20	0	0
T18	0	37	0	0
T19	0	45	0	0
T20	0	14	0	0
T21	0	6	0	0
T22	0	26	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1663	0	0
T13	251007	47	0	0
T14	0	22	0	0
T15	0	8	0	0
T16	0	16	0	0
T17	0	26	0	0
T18	0	30	0	0
T19	0	20	0	0
T20	0	18	0	0
T21	0	29	0	0
T22	0	28	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1613	0	0
T13	251007	35	0	0
T14	0	18	0	0
T15	0	10	0	0
T16	0	16	0	0
T17	0	26	0	0
T18	0	41	0	0
T19	0	18	0	0
T20	0	14	0	0
T21	0	22	0	0
T22	0	24	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1564	0	0
T13	251007	37	0	0
T14	0	15	0	0
T15	0	16	0	0
T16	0	15	0	0
T17	0	16	0	0
T18	0	52	0	0
T19	0	3	0	0
T20	0	12	0	0
T21	0	14	0	0
T22	0	44	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1397	0	0
T13	251007	33	0	0
T14	0	9	0	0
T15	0	22	0	0
T16	0	26	0	0
T17	0	24	0	0
T18	0	51	0	0
T19	0	16	0	0
T20	0	13	0	0
T21	0	16	0	0
T22	0	47	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1066	0	0
T13	251007	55	0	0
T14	0	26	0	0
T15	0	16	0	0
T16	0	21	0	0
T17	0	20	0	0
T18	0	42	0	0
T19	0	34	0	0
T20	0	12	0	0
T21	0	19	0	0
T22	0	33	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1695	0	0
T13	251007	46	0	0
T14	0	18	0	0
T15	0	7	0	0
T16	0	15	0	0
T17	0	17	0	0
T18	0	23	0	0
T19	0	26	0	0
T20	0	17	0	0
T21	0	22	0	0
T22	0	19	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1146	0	0
T13	251007	49	0	0
T14	0	17	0	0
T15	0	24	0	0
T16	0	28	0	0
T17	0	16	0	0
T18	0	25	0	0
T19	0	21	0	0
T20	0	11	0	0
T21	0	13	0	0
T22	0	32	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1397	0	0
T13	251007	44	0	0
T14	0	20	0	0
T15	0	14	0	0
T16	0	31	0	0
T17	0	14	0	0
T18	0	37	0	0
T19	0	22	0	0
T20	0	24	0	0
T21	0	14	0	0
T22	0	36	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1120	0	0
T13	251007	37	0	0
T14	0	35	0	0
T15	0	7	0	0
T16	0	31	0	0
T17	0	17	0	0
T18	0	60	0	0
T19	0	11	0	0
T20	0	13	0	0
T21	0	26	0	0
T22	0	30	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1308	0	0
T13	251007	51	0	0
T14	0	15	0	0
T15	0	6	0	0
T16	0	15	0	0
T17	0	36	0	0
T18	0	41	0	0
T19	0	12	0	0
T20	0	12	0	0
T21	0	31	0	0
T22	0	34	0	0
T23	338673	0	0	0
T24	199897	0	0	0
T25	158101	0	0	0
T26	161907	0	0	0
T27	479412	0	0	0
T28	434560	0	0	0
T29	923425	0	0	0
T30	314620	0	0	0
T31	407128	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1790	0	0
T8	346235	34	0	0
T9	282884	0	0	0
T10	277914	0	0	0
T11	482698	0	0	0
T12	272871	0	0	0
T13	0	63	0	0
T14	0	39	0	0
T15	0	24	0	0
T16	0	16	0	0
T17	0	5	0	0
T18	0	89	0	0
T19	0	26	0	0
T33	0	27	0	0
T34	0	27	0	0
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T37	736274	0	0	0
T38	311551	0	0	0
T39	163543	0	0	0