Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1234464	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1204429

1

T1

893

T2

30

T3

1390

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2141442	1			T1	1679		T3	2538		T4	5155
values[0x0]	148174	1			T1	102		T2	27		T3	146
values[0x1]	149277	1			T1	107		T2	28		T3	153

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	988389	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1450504

1

T1

1091

T2

34

T3

1705

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7571	1			T1	15		T3	20		T4	23
valid_sources[0x01]	11637	1			T1	9		T3	3		T4	19
valid_sources[0x02]	7308	1			T1	16		T3	9		T4	41
valid_sources[0x03]	10574	1			T1	5		T3	17		T4	26
valid_sources[0x04]	8740	1			T1	6		T3	9		T4	23
valid_sources[0x05]	7055	1			T1	5		T3	6		T4	30
valid_sources[0x06]	9251	1			T1	10		T3	12		T4	31
valid_sources[0x07]	9801	1			T1	1		T3	14		T4	15
valid_sources[0x08]	7426	1			T1	9		T3	5		T4	16
valid_sources[0x09]	10613	1			T1	4		T2	1		T3	1
valid_sources[0x0a]	7369	1			T1	11		T3	2		T4	22
valid_sources[0x0b]	7209	1			T1	3		T3	8		T4	31
valid_sources[0x0c]	11805	1			T1	7		T3	6		T4	22
valid_sources[0x0d]	9594	1			T1	6		T4	23		T5	47
valid_sources[0x0e]	7282	1			T1	6		T3	13		T4	26
valid_sources[0x0f]	12443	1			T1	13		T3	13		T4	27
valid_sources[0x10]	13584	1			T1	6		T3	2		T4	22
valid_sources[0x11]	7377	1			T1	6		T4	22		T5	54
valid_sources[0x12]	7378	1			T1	11		T3	2		T4	24
valid_sources[0x13]	9710	1			T1	8		T4	35		T5	23
valid_sources[0x14]	7554	1			T1	10		T3	2		T4	25
valid_sources[0x15]	12103	1			T1	2		T3	8		T4	321
valid_sources[0x16]	7371	1			T1	14		T3	2		T4	27
valid_sources[0x17]	11547	1			T1	16		T3	4		T4	33
valid_sources[0x18]	12624	1			T1	6		T3	10		T4	24
valid_sources[0x19]	7268	1			T1	2		T3	4		T4	31
valid_sources[0x1a]	24305	1			T1	15		T3	7		T4	25
valid_sources[0x1b]	7073	1			T1	1		T2	4		T3	13
valid_sources[0x1c]	11867	1			T1	10		T3	1		T4	13
valid_sources[0x1d]	7522	1			T1	9		T3	7		T4	30
valid_sources[0x1e]	8210	1			T1	9		T3	4		T4	25
valid_sources[0x1f]	20047	1			T1	9		T3	7		T4	31
valid_sources[0x20]	7553	1			T1	3		T3	4		T4	29
valid_sources[0x21]	7038	1			T1	1		T3	7		T4	26
valid_sources[0x22]	8404	1			T1	4		T2	2		T3	6
valid_sources[0x23]	11368	1			T1	4		T3	5		T4	25
valid_sources[0x24]	10972	1			T1	5		T3	4		T4	28
valid_sources[0x25]	7445	1			T1	9		T3	12		T4	29
valid_sources[0x26]	10588	1			T1	5		T3	3		T4	27
valid_sources[0x27]	7298	1			T1	6		T3	3		T4	18
valid_sources[0x28]	11440	1			T1	5		T3	5		T4	25
valid_sources[0x29]	7523	1			T1	3		T3	11		T4	34
valid_sources[0x2a]	10997	1			T1	12		T2	4		T3	9
valid_sources[0x2b]	9847	1			T1	2		T3	6		T4	23
valid_sources[0x2c]	7168	1			T1	2		T3	6		T4	31
valid_sources[0x2d]	7075	1			T1	13		T3	13		T4	36
valid_sources[0x2e]	7310	1			T1	4		T3	13		T4	21
valid_sources[0x2f]	7199	1			T1	4		T3	18		T4	22
valid_sources[0x30]	10070	1			T1	6		T3	9		T4	33
valid_sources[0x31]	11918	1			T1	7		T3	1		T4	25
valid_sources[0x32]	7484	1			T1	20		T3	2		T4	22
valid_sources[0x33]	6866	1			T1	3		T2	2		T3	5
valid_sources[0x34]	8474	1			T1	11		T3	4		T4	14
valid_sources[0x35]	10070	1			T1	15		T3	11		T4	18
valid_sources[0x36]	11097	1			T1	3		T3	6		T4	22
valid_sources[0x37]	8371	1			T3	1		T4	28		T5	61
valid_sources[0x38]	7423	1			T1	5		T3	5		T4	28
valid_sources[0x39]	7203	1			T1	3		T3	1		T4	15
valid_sources[0x3a]	7143	1			T1	11		T3	5		T4	19
valid_sources[0x3b]	8060	1			T1	12		T3	3		T4	29
valid_sources[0x3c]	9253	1			T1	2		T3	5		T4	29
valid_sources[0x3d]	20026	1			T1	5		T3	4		T4	24
valid_sources[0x3e]	8022	1			T1	8		T3	8		T4	23
valid_sources[0x3f]	11331	1			T1	4		T3	2		T4	18
valid_sources[0x40]	7427	1			T1	6		T3	19		T4	33
valid_sources[0x41]	14727	1			T1	5		T3	5		T4	24
valid_sources[0x42]	9082	1			T1	6		T3	3		T4	28
valid_sources[0x43]	7362	1			T1	5		T3	5		T4	25
valid_sources[0x44]	16088	1			T2	1		T3	14		T4	33
valid_sources[0x45]	13928	1			T1	6		T3	2		T4	26
valid_sources[0x46]	11851	1			T1	5		T3	9		T4	38
valid_sources[0x47]	10415	1			T1	12		T3	6		T4	30
valid_sources[0x48]	11546	1			T1	14		T3	14		T4	32
valid_sources[0x49]	8250	1			T1	8		T3	8		T4	23
valid_sources[0x4a]	21243	1			T1	10		T3	6		T4	32
valid_sources[0x4b]	7337	1			T1	8		T3	12		T4	26
valid_sources[0x4c]	11667	1			T1	10		T2	1		T3	6
valid_sources[0x4d]	11148	1			T1	5		T3	12		T4	31
valid_sources[0x4e]	9932	1			T1	6		T3	5		T4	22
valid_sources[0x4f]	15933	1			T1	6		T3	1		T4	23
valid_sources[0x50]	10837	1			T1	7		T3	3		T4	31
valid_sources[0x51]	7133	1			T1	6		T3	8		T4	46
valid_sources[0x52]	7085	1			T1	2		T3	6		T4	26
valid_sources[0x53]	11366	1			T1	13		T3	1		T4	31
valid_sources[0x54]	12410	1			T1	7		T3	5		T4	24
valid_sources[0x55]	7284	1			T1	8		T3	12		T4	18
valid_sources[0x56]	7140	1			T1	4		T3	9		T4	24
valid_sources[0x57]	6947	1			T1	3		T3	6		T4	21
valid_sources[0x58]	7206	1			T1	11		T3	25		T4	16
valid_sources[0x59]	11312	1			T1	1		T3	10		T4	20
valid_sources[0x5a]	7418	1			T1	7		T3	2		T4	25
valid_sources[0x5b]	7738	1			T1	8		T3	7		T4	27
valid_sources[0x5c]	7408	1			T1	12		T3	6		T4	32
valid_sources[0x5d]	7128	1			T1	4		T3	2		T4	23
valid_sources[0x5e]	7319	1			T1	10		T3	9		T4	30
valid_sources[0x5f]	7188	1			T1	10		T3	5		T4	13
valid_sources[0x60]	14126	1			T1	5		T2	1		T3	3
valid_sources[0x61]	7118	1			T1	4		T3	8		T4	35
valid_sources[0x62]	7176	1			T1	8		T3	4		T4	19
valid_sources[0x63]	7138	1			T1	6		T3	2		T4	22
valid_sources[0x64]	6891	1			T1	5		T3	6		T4	25
valid_sources[0x65]	7894	1			T1	5		T2	2		T3	4
valid_sources[0x66]	7499	1			T1	20		T3	9		T4	33
valid_sources[0x67]	11491	1			T1	6		T3	9		T4	23
valid_sources[0x68]	16750	1			T1	8		T3	4		T4	26
valid_sources[0x69]	8115	1			T1	3		T3	3		T4	35
valid_sources[0x6a]	7131	1			T1	5		T3	7		T4	24
valid_sources[0x6b]	11806	1			T1	12		T3	11		T4	18
valid_sources[0x6c]	6924	1			T1	6		T3	9		T4	31
valid_sources[0x6d]	25358	1			T1	9		T3	15		T4	22
valid_sources[0x6e]	13167	1			T1	2		T3	15		T4	23
valid_sources[0x6f]	11365	1			T1	10		T3	8		T4	34
valid_sources[0x70]	8315	1			T1	7		T3	5		T4	28
valid_sources[0x71]	13619	1			T1	7		T2	2		T3	5
valid_sources[0x72]	7500	1			T1	7		T3	4		T4	22
valid_sources[0x73]	7808	1			T1	10		T2	2		T3	8
valid_sources[0x74]	8227	1			T1	6		T3	7		T4	30
valid_sources[0x75]	7443	1			T1	6		T3	15		T4	37
valid_sources[0x76]	7628	1			T1	6		T2	2		T3	13
valid_sources[0x77]	7264	1			T1	18		T3	3		T4	25
valid_sources[0x78]	7913	1			T1	10		T3	6		T4	20
valid_sources[0x79]	9649	1			T1	12		T3	8		T4	21
valid_sources[0x7a]	8015	1			T1	7		T2	1		T3	7
valid_sources[0x7b]	7116	1			T1	5		T2	1		T3	4
valid_sources[0x7c]	6991	1			T1	21		T3	7		T4	26
valid_sources[0x7d]	8102	1			T1	7		T3	14		T4	27
valid_sources[0x7e]	10659	1			T1	2		T3	3		T4	29
valid_sources[0x7f]	9882	1			T1	11		T3	7		T4	26
valid_sources[0x80]	13529	1			T1	2		T3	7		T4	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1066027

1

T1

799

T3

1233

T4

2569

values[0x0]

all_enables

biggest_size

80364

1

T1

56

T2

15

T3

91

values[0x1]

all_enables

biggest_size

58038

1

T1

38

T2

15

T3

66