Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28023	1			T1	10		T3	26		T4	367
auto[PWRUP]	113	1			T6	1		T8	1		T12	2
auto[ONEST_0]	74	1			T6	2		T12	2		T183	1
auto[ONEST_021]	23	1			T4	2		T12	1		T66	1
auto[ONEST_1]	71	1			T8	1		T12	1		T66	1
auto[ONEST_DONE]	3	1			T224	1		T225	1		T226	1
auto[LP_0]	131	1			T4	5		T6	2		T8	1
auto[LP_021]	33	1			T4	1		T6	1		T227	1
auto[LP_1]	124	1			T4	1		T8	1		T12	1
auto[LP_EVAL]	70	1			T6	2		T55	1		T66	1
auto[LP_SLP]	565	1			T4	11		T6	14		T8	4
auto[LP_PWRUP]	30	1			T12	2		T55	1		T65	1
auto[NP_0]	161	1			T4	3		T6	4		T8	1
auto[NP_021]	30	1			T4	2		T8	1		T12	2
auto[NP_1]	147	1			T4	2		T6	4		T12	2
auto[NP_EVAL]	34	1			T6	1		T55	1		T66	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T4

1

T6

1

T12

2

min

27598

1

T1

10

T3

26

T4

358

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27613	1			T1	10		T3	26		T4	358
pow[0x1]	15	1			T8	1		T183	1		T66	1
pow[0x2]	10	1			T12	1		T228	1		T224	1
pow[0x3]	35	1			T12	2		T65	3		T229	1
pow[0x4]	66	1			T4	3		T6	1		T12	1
pow[0x5]	135	1			T4	1		T6	2		T8	1
pow[0x6]	238	1			T4	5		T6	4		T8	2
pow[0x7]	518	1			T4	10		T6	7		T8	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

207

1

T4

6

T6

2

T8

1

min

27063

1

T1

10

T3

26

T4

347

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27063	1			T1	10		T3	26		T4	347
pow[0x3]	1	1			T230	1		-	-		-	-
pow[0x6]	2	1			T231	1		T232	1		-	-
pow[0x8]	6	1			T233	1		T228	1		T53	1
pow[0x9]	10	1			T65	1		T224	1		T234	1
pow[0xa]	25	1			T4	1		T6	2		T66	1
pow[0xb]	34	1			T12	2		T55	1		T66	1
pow[0xc]	81	1			T6	1		T8	3		T12	2
pow[0xd]	148	1			T4	5		T6	2		T12	3
pow[0xe]	286	1			T4	5		T6	7		T8	3
pow[0xf]	592	1			T4	10		T6	3		T8	2