Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	100.00	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	0	45	100.00

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2333	1			T4	23		T6	16		T8	12
auto[PWRUP]	137	1			T4	1		T6	1		T8	3
auto[ONEST_0]	64	1			T8	1		T12	2		T183	1
auto[ONEST_021]	14	1			T12	1		T65	1		T49	1
auto[ONEST_1]	91	1			T6	1		T8	1		T12	1
auto[ONEST_DONE]	3	1			T102	1		T344	1		T345	1
auto[LP_0]	118	1			T4	2		T6	1		T55	3
auto[LP_021]	25	1			T65	1		T229	1		T346	1
auto[LP_1]	138	1			T6	2		T8	2		T12	3
auto[LP_EVAL]	53	1			T4	2		T12	1		T55	1
auto[LP_SLP]	521	1			T4	7		T6	6		T8	3
auto[LP_PWRUP]	27	1			T6	1		T183	1		T227	1
auto[NP_0]	240	1			T4	4		T6	4		T8	2
auto[NP_021]	65	1			T6	2		T12	2		T55	1
auto[NP_1]	220	1			T4	2		T6	2		T8	3
auto[NP_EVAL]	38	1			T4	3		T46	1		T229	1
auto[NP_DONE]	1	1			T347	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T6

1

T8

1

T55

1

min

2011

1

T4

13

T6

8

T8

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2019	1			T4	13		T6	8		T8	5
pow[0x1]	10	1			T39	1		T52	1		T53	1
pow[0x2]	15	1			T65	1		T242	1		T225	1
pow[0x3]	40	1			T4	1		T6	1		T8	1
pow[0x4]	70	1			T4	2		T6	1		T12	2
pow[0x5]	144	1			T4	2		T6	1		T8	1
pow[0x6]	283	1			T4	3		T6	5		T8	3
pow[0x7]	486	1			T4	6		T6	9		T8	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

193

1

T4

3

T8

2

T12

5

min

1417

1

T4

11

T6

4

T8

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1422	1			T4	11		T6	4		T8	2
pow[0x1]	19	1			T46	4		T51	1		T309	1
pow[0x2]	25	1			T47	5		T50	1		T51	1
pow[0x3]	56	1			T12	3		T47	1		T54	4
pow[0x4]	54	1			T12	4		T49	1		T51	2
pow[0x5]	4	1			T348	1		T349	1		T350	1
pow[0x6]	4	1			T351	2		T347	1		T352	1
pow[0x7]	2	1			T242	1		T353	1		-	-
pow[0x8]	6	1			T228	1		T34	1		T225	1
pow[0x9]	9	1			T354	1		T228	1		T102	1
pow[0xa]	16	1			T6	1		T346	1		T227	1
pow[0xb]	34	1			T4	1		T354	1		T346	1
pow[0xc]	76	1			T8	2		T55	1		T183	1
pow[0xd]	160	1			T4	2		T6	2		T8	1
pow[0xe]	284	1			T4	7		T6	4		T8	2
pow[0xf]	551	1			T4	6		T6	6		T8	6