Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2149	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2004	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2140	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2057	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2257	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2233	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2246	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2100	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2092	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2292	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2038	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2199	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2288	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2149	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2105	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2319	0	0
adc_en_ctl_rd_A	2147483647	1721	0	0
adc_fsm_rst_rd_A	2147483647	1560	0	0
adc_intr_ctl_rd_A	2147483647	2228	0	0
adc_lp_sample_ctl_rd_A	2147483647	1593	0	0
adc_pd_ctl_rd_A	2147483647	1943	0	0
adc_sample_ctl_rd_A	2147483647	1586	0	0
adc_wakeup_ctl_rd_A	2147483647	1684	0	0
intr_enable_rd_A	2147483647	2163	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2149	0	0
T13	677615	35	0	0
T14	0	23	0	0
T15	0	34	0	0
T16	0	9	0	0
T17	0	21	0	0
T18	0	15	0	0
T19	0	18	0	0
T20	0	29	0	0
T21	0	44	0	0
T22	0	32	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2004	0	0
T13	677615	58	0	0
T14	0	15	0	0
T15	0	24	0	0
T16	0	6	0	0
T17	0	17	0	0
T18	0	21	0	0
T19	0	8	0	0
T20	0	24	0	0
T21	0	31	0	0
T22	0	26	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2140	0	0
T13	677615	43	0	0
T14	0	18	0	0
T15	0	30	0	0
T16	0	16	0	0
T17	0	42	0	0
T18	0	6	0	0
T19	0	10	0	0
T20	0	29	0	0
T21	0	41	0	0
T22	0	34	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2057	0	0
T13	677615	34	0	0
T14	0	15	0	0
T15	0	27	0	0
T16	0	23	0	0
T17	0	31	0	0
T18	0	19	0	0
T19	0	8	0	0
T20	0	16	0	0
T21	0	34	0	0
T22	0	27	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2257	0	0
T13	677615	35	0	0
T14	0	12	0	0
T15	0	42	0	0
T16	0	20	0	0
T17	0	34	0	0
T18	0	13	0	0
T19	0	11	0	0
T20	0	6	0	0
T21	0	32	0	0
T22	0	9	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2233	0	0
T13	677615	52	0	0
T14	0	25	0	0
T15	0	28	0	0
T16	0	5	0	0
T17	0	19	0	0
T18	0	21	0	0
T19	0	8	0	0
T20	0	8	0	0
T21	0	42	0	0
T22	0	28	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2246	0	0
T13	677615	21	0	0
T14	0	23	0	0
T15	0	18	0	0
T16	0	9	0	0
T17	0	21	0	0
T18	0	13	0	0
T19	0	20	0	0
T20	0	25	0	0
T21	0	45	0	0
T22	0	20	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2100	0	0
T13	677615	36	0	0
T14	0	29	0	0
T15	0	21	0	0
T16	0	19	0	0
T17	0	33	0	0
T18	0	23	0	0
T19	0	7	0	0
T20	0	20	0	0
T21	0	27	0	0
T22	0	18	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2092	0	0
T13	677615	46	0	0
T14	0	18	0	0
T15	0	32	0	0
T16	0	19	0	0
T17	0	24	0	0
T18	0	9	0	0
T19	0	8	0	0
T20	0	23	0	0
T21	0	35	0	0
T22	0	34	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2292	0	0
T13	677615	47	0	0
T14	0	18	0	0
T15	0	35	0	0
T16	0	2	0	0
T17	0	25	0	0
T18	0	23	0	0
T19	0	8	0	0
T20	0	20	0	0
T21	0	42	0	0
T22	0	38	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2038	0	0
T13	677615	14	0	0
T14	0	16	0	0
T15	0	38	0	0
T16	0	22	0	0
T17	0	32	0	0
T18	0	9	0	0
T19	0	9	0	0
T20	0	17	0	0
T21	0	38	0	0
T22	0	39	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2199	0	0
T13	677615	36	0	0
T14	0	22	0	0
T15	0	39	0	0
T16	0	6	0	0
T17	0	38	0	0
T18	0	5	0	0
T19	0	5	0	0
T20	0	23	0	0
T21	0	33	0	0
T22	0	31	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2288	0	0
T13	677615	19	0	0
T14	0	11	0	0
T15	0	44	0	0
T16	0	21	0	0
T17	0	38	0	0
T18	0	12	0	0
T19	0	24	0	0
T20	0	18	0	0
T21	0	29	0	0
T22	0	22	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2149	0	0
T13	677615	36	0	0
T14	0	12	0	0
T15	0	34	0	0
T16	0	13	0	0
T17	0	36	0	0
T18	0	12	0	0
T19	0	15	0	0
T20	0	24	0	0
T21	0	33	0	0
T22	0	32	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2105	0	0
T13	677615	39	0	0
T14	0	27	0	0
T15	0	28	0	0
T16	0	11	0	0
T17	0	45	0	0
T18	0	9	0	0
T19	0	22	0	0
T20	0	22	0	0
T21	0	40	0	0
T22	0	28	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2319	0	0
T13	677615	41	0	0
T14	0	20	0	0
T15	0	36	0	0
T16	0	11	0	0
T17	0	42	0	0
T18	0	16	0	0
T19	0	15	0	0
T20	0	28	0	0
T21	0	39	0	0
T22	0	24	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1721	0	0
T13	677615	34	0	0
T14	0	13	0	0
T15	0	41	0	0
T16	0	26	0	0
T17	0	36	0	0
T18	0	17	0	0
T19	0	14	0	0
T20	0	10	0	0
T21	0	37	0	0
T22	0	16	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1560	0	0
T13	677615	30	0	0
T14	0	18	0	0
T15	0	25	0	0
T16	0	17	0	0
T17	0	41	0	0
T18	0	17	0	0
T19	0	18	0	0
T20	0	11	0	0
T21	0	28	0	0
T22	0	27	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2228	0	0
T13	677615	30	0	0
T14	0	21	0	0
T15	0	47	0	0
T16	0	22	0	0
T17	0	32	0	0
T18	0	20	0	0
T19	0	21	0	0
T20	0	31	0	0
T21	0	39	0	0
T22	0	11	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1593	0	0
T13	677615	45	0	0
T14	0	12	0	0
T15	0	40	0	0
T16	0	10	0	0
T17	0	31	0	0
T18	0	34	0	0
T19	0	12	0	0
T20	0	10	0	0
T21	0	41	0	0
T22	0	43	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1943	0	0
T13	677615	28	0	0
T14	0	23	0	0
T15	0	43	0	0
T16	0	23	0	0
T17	0	39	0	0
T18	0	17	0	0
T19	0	5	0	0
T20	0	14	0	0
T21	0	39	0	0
T22	0	34	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1586	0	0
T13	677615	27	0	0
T14	0	28	0	0
T15	0	40	0	0
T16	0	16	0	0
T17	0	17	0	0
T18	0	16	0	0
T19	0	2	0	0
T20	0	23	0	0
T21	0	24	0	0
T22	0	23	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1684	0	0
T13	677615	46	0	0
T14	0	8	0	0
T15	0	32	0	0
T16	0	15	0	0
T17	0	32	0	0
T18	0	10	0	0
T19	0	12	0	0
T20	0	19	0	0
T21	0	33	0	0
T22	0	33	0	0
T23	861421	0	0	0
T24	75566	0	0	0
T25	50214	0	0	0
T26	369761	0	0	0
T27	155663	0	0	0
T28	187605	0	0	0
T29	415286	0	0	0
T30	321511	0	0	0
T31	10223	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2163	0	0
T13	0	29	0	0
T14	0	14	0	0
T15	0	40	0	0
T16	0	24	0	0
T28	0	26	0	0
T32	165115	19	0	0
T33	0	15	0	0
T34	0	5	0	0
T35	0	53	0	0
T36	0	24	0	0
T37	665110	0	0	0
T38	390810	0	0	0
T39	220227	0	0	0
T40	582581	0	0	0
T41	156471	0	0	0
T42	858346	0	0	0
T43	132741	0	0	0
T44	786327	0	0	0
T45	118796	0	0	0