Group : push_pull_agent_pkg::req_ack_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : push_pull_agent_pkg::req_ack_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_push_pull_agent_0.1/push_pull_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
push_pull_agent_pkg.uvm_test_top.env.m_adc_push_pull_agent_0.cov::m_req_ack_cg 100.00 1 100 1 64 64
push_pull_agent_pkg.uvm_test_top.env.m_adc_push_pull_agent_1.cov::m_req_ack_cg 100.00 1 100 1 64 64




Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_adc_push_pull_agent_0.cov::m_req_ack_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_adc_push_pull_agent_0.cov::m_req_ack_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_adc_push_pull_agent_0.cov::m_req_ack_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_ack 3 0 3 100.00 100 1 1 4



Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_adc_push_pull_agent_1.cov::m_req_ack_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_adc_push_pull_agent_1.cov::m_req_ack_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_adc_push_pull_agent_1.cov::m_req_ack_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_ack 3 0 3 100.00 100 1 1 4


Summary for Variable cp_req_ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins
NAMECOUNTSTATUS
ack_wo_req 0 Excluded
[auto[1]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 783489 1 T1 1685 T2 1645 T3 2524
auto[2] 781620 1 T1 1684 T2 1643 T3 2521
auto[3] 777209 1 T1 1683 T2 1641 T3 2518


Summary for Variable cp_req_ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins
NAMECOUNTSTATUS
ack_wo_req 0 Excluded
[auto[1]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 776741 1 T1 1683 T2 1641 T3 2518
auto[2] 776964 1 T1 1683 T2 1641 T3 2518
auto[3] 776198 1 T1 1683 T2 1641 T3 2518

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%