Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1217760	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1188925

1

T1

916

T2

942

T3

1424

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2110948	1			T1	1686		T2	1644		T3	2522
values[0x0]	147671	1			T1	102		T2	106		T3	155
values[0x1]	148066	1			T1	106		T2	94		T3	152

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	975955	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1430730

1

T1

1137

T2

1101

T3

1673

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7950	1			T1	6		T2	5		T4	8
valid_sources[0x01]	9500	1			T1	5		T2	17		T4	13
valid_sources[0x02]	7773	1			T1	12		T2	10		T4	20
valid_sources[0x03]	7538	1			T1	3		T2	6		T4	24
valid_sources[0x04]	10112	1			T1	5		T2	1		T4	24
valid_sources[0x05]	6545	1			T1	7		T2	7		T4	36
valid_sources[0x06]	11375	1			T1	5		T2	5		T4	13
valid_sources[0x07]	13922	1			T1	5		T2	8		T4	20
valid_sources[0x08]	6619	1			T1	2		T2	9		T4	18
valid_sources[0x09]	10972	1			T1	3		T2	10		T4	22
valid_sources[0x0a]	7005	1			T1	33		T2	5		T4	5
valid_sources[0x0b]	6794	1			T1	1		T2	3		T4	24
valid_sources[0x0c]	15144	1			T1	3		T2	4		T4	12
valid_sources[0x0d]	11689	1			T1	4		T2	2		T4	24
valid_sources[0x0e]	19471	1			T1	6		T2	6		T4	26
valid_sources[0x0f]	7854	1			T1	3		T2	4		T4	6
valid_sources[0x10]	9050	1			T2	9		T4	13		T5	3
valid_sources[0x11]	7003	1			T1	2		T2	8		T4	12
valid_sources[0x12]	7058	1			T1	3		T2	6		T4	13
valid_sources[0x13]	6849	1			T1	1		T2	5		T4	20
valid_sources[0x14]	15450	1			T1	4		T2	6		T4	17
valid_sources[0x15]	12085	1			T1	1		T2	9		T4	19
valid_sources[0x16]	6783	1			T1	5		T2	6		T4	14
valid_sources[0x17]	6751	1			T1	6		T2	6		T4	20
valid_sources[0x18]	8945	1			T2	5		T4	21		T5	6
valid_sources[0x19]	9149	1			T1	2		T2	5		T4	10
valid_sources[0x1a]	12513	1			T1	6		T2	14		T4	9
valid_sources[0x1b]	7381	1			T1	5		T2	1		T4	15
valid_sources[0x1c]	8548	1			T1	2		T2	7		T4	15
valid_sources[0x1d]	6335	1			T1	2		T2	6		T4	23
valid_sources[0x1e]	7437	1			T1	7		T2	3		T4	13
valid_sources[0x1f]	11165	1			T1	11		T2	5		T4	21
valid_sources[0x20]	6262	1			T1	7		T2	8		T4	14
valid_sources[0x21]	9011	1			T1	1		T2	10		T4	21
valid_sources[0x22]	8443	1			T1	7		T2	7		T4	11
valid_sources[0x23]	6889	1			T1	5		T2	3		T4	17
valid_sources[0x24]	15791	1			T1	1		T2	5		T4	16
valid_sources[0x25]	7988	1			T1	7		T2	10		T4	17
valid_sources[0x26]	9883	1			T1	3		T2	5		T4	15
valid_sources[0x27]	7542	1			T1	4		T2	7		T4	16
valid_sources[0x28]	7001	1			T1	10		T2	4		T4	16
valid_sources[0x29]	6962	1			T1	7		T2	9		T4	14
valid_sources[0x2a]	12032	1			T1	5		T2	8		T4	21
valid_sources[0x2b]	6411	1			T1	2		T2	5		T4	14
valid_sources[0x2c]	6826	1			T1	3		T2	4		T4	12
valid_sources[0x2d]	7536	1			T1	4		T2	6		T4	21
valid_sources[0x2e]	11042	1			T1	4		T2	5		T4	18
valid_sources[0x2f]	7482	1			T1	4		T2	5		T4	18
valid_sources[0x30]	12166	1			T1	1		T2	5		T4	26
valid_sources[0x31]	9594	1			T1	2		T2	5		T4	8
valid_sources[0x32]	7233	1			T1	2		T2	14		T4	23
valid_sources[0x33]	7521	1			T1	46		T2	6		T4	14
valid_sources[0x34]	11401	1			T1	30		T2	6		T4	11
valid_sources[0x35]	6829	1			T1	4		T2	5		T4	14
valid_sources[0x36]	12229	1			T1	9		T2	8		T4	18
valid_sources[0x37]	9575	1			T1	6		T2	7		T3	2829
valid_sources[0x38]	13585	1			T1	1		T2	9		T4	10
valid_sources[0x39]	9385	1			T1	4		T2	6		T4	16
valid_sources[0x3a]	6577	1			T1	5		T2	7		T4	22
valid_sources[0x3b]	7063	1			T1	3		T2	8		T4	28
valid_sources[0x3c]	6235	1			T1	8		T2	6		T4	17
valid_sources[0x3d]	7681	1			T1	1		T2	4		T4	12
valid_sources[0x3e]	6479	1			T1	6		T2	7		T4	21
valid_sources[0x3f]	10795	1			T1	3		T2	12		T4	15
valid_sources[0x40]	11231	1			T1	1		T2	13		T4	19
valid_sources[0x41]	6554	1			T2	5		T4	8		T5	1
valid_sources[0x42]	11342	1			T2	9		T4	17		T5	1
valid_sources[0x43]	11387	1			T1	4		T2	5		T4	8
valid_sources[0x44]	13671	1			T1	79		T2	2		T4	29
valid_sources[0x45]	6725	1			T1	4		T2	7		T4	18
valid_sources[0x46]	6580	1			T1	4		T2	5		T4	13
valid_sources[0x47]	8756	1			T1	66		T2	5		T4	23
valid_sources[0x48]	9694	1			T1	6		T2	6		T4	16
valid_sources[0x49]	6682	1			T1	5		T2	6		T4	12
valid_sources[0x4a]	7114	1			T1	5		T2	7		T4	26
valid_sources[0x4b]	7359	1			T1	42		T2	15		T4	11
valid_sources[0x4c]	9642	1			T1	3		T2	11		T4	12
valid_sources[0x4d]	7654	1			T1	7		T2	7		T4	21
valid_sources[0x4e]	6947	1			T1	15		T2	10		T4	19
valid_sources[0x4f]	6683	1			T1	4		T2	7		T4	7
valid_sources[0x50]	9663	1			T1	4		T2	10		T4	23
valid_sources[0x51]	9576	1			T1	3		T2	6		T4	18
valid_sources[0x52]	7885	1			T1	7		T2	8		T4	23
valid_sources[0x53]	9701	1			T1	13		T2	8		T4	10
valid_sources[0x54]	13585	1			T1	70		T2	9		T4	17
valid_sources[0x55]	6947	1			T1	46		T2	6		T4	19
valid_sources[0x56]	9726	1			T1	8		T2	9		T4	15
valid_sources[0x57]	6995	1			T2	6		T4	18		T5	4
valid_sources[0x58]	8961	1			T1	7		T2	5		T4	24
valid_sources[0x59]	10671	1			T1	5		T2	9		T4	16
valid_sources[0x5a]	11263	1			T1	3		T2	5		T4	11
valid_sources[0x5b]	7911	1			T1	7		T2	5		T4	26
valid_sources[0x5c]	15957	1			T1	7		T2	13		T4	15
valid_sources[0x5d]	16064	1			T1	3		T2	11		T4	20
valid_sources[0x5e]	6167	1			T1	60		T2	4		T4	15
valid_sources[0x5f]	12515	1			T1	5		T2	18		T4	15
valid_sources[0x60]	11166	1			T1	3		T2	6		T4	15
valid_sources[0x61]	17285	1			T1	4		T2	11		T4	18
valid_sources[0x62]	7073	1			T1	9		T2	6		T4	24
valid_sources[0x63]	7008	1			T1	7		T2	4		T4	9
valid_sources[0x64]	6848	1			T1	45		T2	5		T4	11
valid_sources[0x65]	11015	1			T2	5		T4	12		T6	13
valid_sources[0x66]	11015	1			T1	1		T2	6		T4	15
valid_sources[0x67]	14978	1			T1	29		T2	14		T4	17
valid_sources[0x68]	7090	1			T1	2		T2	6		T4	14
valid_sources[0x69]	6611	1			T1	4		T2	11		T4	15
valid_sources[0x6a]	7919	1			T1	1		T2	2		T4	20
valid_sources[0x6b]	8700	1			T1	4		T2	5		T4	23
valid_sources[0x6c]	6840	1			T1	5		T2	4		T4	12
valid_sources[0x6d]	25861	1			T1	2		T2	7		T4	17
valid_sources[0x6e]	14578	1			T1	3		T2	10		T4	20
valid_sources[0x6f]	6719	1			T1	1		T2	5		T4	19
valid_sources[0x70]	12037	1			T1	2		T2	3		T4	17
valid_sources[0x71]	11933	1			T1	2		T2	9		T4	8
valid_sources[0x72]	6798	1			T1	1		T2	9		T4	10
valid_sources[0x73]	6603	1			T2	7		T4	18		T6	10
valid_sources[0x74]	8557	1			T1	10		T2	4		T4	16
valid_sources[0x75]	7866	1			T1	19		T2	12		T4	22
valid_sources[0x76]	6614	1			T1	21		T2	7		T4	15
valid_sources[0x77]	9221	1			T1	6		T2	10		T4	19
valid_sources[0x78]	6818	1			T1	4		T2	11		T4	14
valid_sources[0x79]	6985	1			T1	18		T2	5		T4	14
valid_sources[0x7a]	6612	1			T1	45		T2	12		T4	18
valid_sources[0x7b]	7107	1			T1	4		T2	9		T4	20
valid_sources[0x7c]	7834	1			T1	4		T2	8		T4	18
valid_sources[0x7d]	8567	1			T1	2		T2	4		T4	19
valid_sources[0x7e]	15416	1			T1	11		T2	2		T4	9
valid_sources[0x7f]	6477	1			T1	6		T2	5		T4	9
valid_sources[0x80]	7338	1			T1	5		T2	5		T4	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1051610

1

T1

817

T2

837

T3

1267

values[0x0]

all_enables

biggest_size

79897

1

T1

55

T2

60

T3

92

values[0x1]

all_enables

biggest_size

57418

1

T1

44

T2

45

T3

65