Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28830	1			T1	17		T2	15		T3	29
auto[PWRUP]	132	1			T12	2		T47	2		T48	1
auto[ONEST_0]	85	1			T5	2		T47	1		T48	2
auto[ONEST_021]	14	1			T53	1		T51	1		T199	1
auto[ONEST_1]	67	1			T5	1		T200	1		T53	1
auto[ONEST_DONE]	4	1			T53	1		T201	1		T202	1
auto[LP_0]	128	1			T5	2		T12	1		T48	1
auto[LP_021]	27	1			T12	1		T48	1		T49	1
auto[LP_1]	108	1			T5	1		T12	1		T48	1
auto[LP_EVAL]	78	1			T12	1		T47	3		T48	1
auto[LP_SLP]	538	1			T5	5		T12	7		T47	3
auto[LP_PWRUP]	27	1			T48	1		T51	1		T41	1
auto[NP_0]	171	1			T5	2		T12	3		T47	2
auto[NP_021]	43	1			T53	1		T203	1		T84	1
auto[NP_1]	158	1			T5	1		T12	3		T48	1
auto[NP_EVAL]	36	1			T48	1		T49	1		T53	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T204

1

T205

1

T206

1

min

28307

1

T1

17

T2

15

T3

29

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28321	1			T1	17		T2	15		T3	29
pow[0x1]	6	1			T48	1		T206	1		T207	1
pow[0x2]	13	1			T203	1		T208	1		T206	1
pow[0x3]	27	1			T48	1		T200	2		T15	1
pow[0x4]	76	1			T5	2		T48	2		T49	1
pow[0x5]	133	1			T5	2		T12	1		T47	2
pow[0x6]	281	1			T12	2		T47	2		T48	5
pow[0x7]	530	1			T5	6		T12	7		T47	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

188

1

T5

2

T47

2

T48

3

min

27835

1

T1

17

T2

15

T3

29

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27835	1			T1	17		T2	15		T3	29
pow[0x4]	1	1			T209	1		-	-		-	-
pow[0x7]	1	1			T210	1		-	-		-	-
pow[0x8]	2	1			T211	1		T212	1		-	-
pow[0x9]	9	1			T199	1		T205	1		T213	1
pow[0xa]	15	1			T200	1		T49	1		T53	1
pow[0xb]	46	1			T48	1		T49	1		T53	1
pow[0xc]	79	1			T12	1		T48	2		T53	2
pow[0xd]	142	1			T5	1		T12	2		T47	1
pow[0xe]	322	1			T5	2		T12	5		T47	2
pow[0xf]	580	1			T5	7		T12	5		T47	5